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An Instruction Set Extension for Fast and Memory-Efficient AES Implementation

  • Stefan Tillich
  • Johann Großschädl
  • Alexander Szekely
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3677)

Abstract

As more and more security-critical computation is done in embedded systems it is also becoming increasingly important to facilitate cryptography in such systems. The Advanced Encryption Standard (AES) specifies one of the most important cryptographic algorithms today and has received a lot of attention from researchers. Most prior work has focused on efficient implementations with throughput as main criterion. However, AES implementations in small and constrained environments require additional factors to be accounted for, such as limited memory and energy supply. In this paper we present an inexpensive extension to a 32-bit general-purpose processor which allows compact and fast AES implementations. We have integrated this extension into the SPARC V8-compatible LEON-2 processor and measured a speedup by a factor of up to 1.43 for encryption and 1.3 for decryption. At the same time the code size has been reduced by 30–40%.

Keywords

Advanced Encryption Standard 32-bit implementation instruction set extensions S-box cache-based side-channel analysis 

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Copyright information

© IFIP International Federation for Information Processing 2005

Authors and Affiliations

  • Stefan Tillich
    • 1
  • Johann Großschädl
    • 1
  • Alexander Szekely
    • 1
  1. 1.Institute for Applied Information Processing and CommunicationsGraz University of TechnologyGrazAustria

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