Abstract
There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip evolutionary system with the evolutionary algorithm implemented in software on a built-in processor. This architecture is implemented in a Xilinx Virtex-II Pro FPGA with an embedded PowerPC processor. This allows for a rapid processing of the time consuming parts in hardware and leaving other parts to more easily modifiable software. This platform will be beneficial for future work regarding both cost and compactness. Experiments have been performed on the physical device with software running in parallel with fitness computation in digital logic. The results show that the system uses only twice as much time when compared to a PC running at 10 times faster clock speed.
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References
Goldberg, D.: Genetic Algorithms in search, optimization, and machine learning. Addison-Wesley, Reading (1989)
Kajitani, I., et al.: A myoelectric controlled prosthetic hand with an evolvable hardware lsi chip. Technology and Disability 15(2), 129–143 (2003)
Kajitani, I., Hoshino, T., Kajihara, N., Iwata, M., Higuchi, T.: An evolvable hardware chip and its application as a multi-function prosthetic hand controller. In: Proc. of 16th National Conference on Artificial Intelligence (AAAI 1999), pp. 182–187 (1999)
Kalganova, T.: Bidirectional incremental evolution in extrinsic evolvable hardware. In: Lohn, J., et al. (eds.) Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 65–74. IEEE Computer Society, Los Alamitos (2000)
Miller, J.F., Job, D., Vassilev, V.K.: Principles in the evolutionary design of digital circuits – Part I. Journal of Genetic Programming and Evolvable Machines 1(1), 8–35 (2000)
Perkins, S., Porter, P., Harvey, N.: Self-contained spatially-structured genetic algorithm for signal processing. In: Miller, J., et al. (eds.) Evolvable Systems: From Biology to Hardware. Third International Conference, ICES 2000. LNCS, vol. 1801, pp. 165–174. Springer, Heidelberg (2000)
Roggen, D., Thoma, Y., Sanchez, E.: An evolving and developing cellular electronic circuit. In: Pollack, J., Bedau, M., Husbands, P., Ikegami, T., Watson, R.A. (eds.) ALife9: Proceedings of the Ninth International Conference on Artificial Life, Boston, MA, pp. 33–38. MIT Press, Cambridge (2004)
Schmitz, T., et al.: Speeding up hardware evolution: A coprocessor for evolutionary algorithms. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 274–285. Springer, Heidelberg (2003)
Sekanina, L., Friedl, S.: On routine implementation of virtual evolvable devices using combo6. In: Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware, pp. 63–70. IEEE, Los Alamitos (2004)
Shackleford, B., et al.: A high-performance, pipelined, FPGA-based genetic algorithm machine. Journal of Genetic Programming and Evolvable Machines 2(1), 33–60 (2001)
Torresen, J.: Evolving multiplier circuits by training set and training vector partitioning. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 228–237. Springer, Heidelberg (2003)
Tufte, G., Haddow, P.C.: Prototyping a ga pipeline for complete hardware evolution. In: 1st NASA / DoD Workshop on Evolvable Hardware (EH 1999), pp. 18–25 (1999)
Job, D., Vassilev, V., Miller, J.: Towards the automatic design of more efficient digital circuits. In: Lohn, J., et al. (eds.) Proc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, July 2000, pp. 151–160. IEEE Computer Society, Los Alamitos (2000)
Xilinx Inc. PowerPC 405 Processor Block Reference Guide (August 2004)
Xilinx Inc. Embedded System Tools Reference Manual (February 2005)
Xilinx Inc. Processor IP Reference Guide (February 2005)
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Glette, K., Torresen, J. (2005). A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. In: Moreno, J.M., Madrenas, J., Cosp, J. (eds) Evolvable Systems: From Biology to Hardware. ICES 2005. Lecture Notes in Computer Science, vol 3637. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11549703_7
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DOI: https://doi.org/10.1007/11549703_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28736-0
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