Abstract
A design of system area network interface card (NIC) based on the Intel IOP310 I/O processor chipset is proposed in this paper. The chipset makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. A network interface unit (NIU) based on memory bus is embedded in the NIC. The NIU not only thoroughly compensates for the lack of high performance data transfer channel in the embedded system, but also efficiently utilizes the memory bus bandwidth and direct memory access (DMA) engine to reduce the latency for data transfer between the host and network. The NIC is a part of DCNet, which is the system area network (SAN) of Dawning 4000A Cluster. The testing results of DCNet show that the NIC obtains competitive communication performance compared with Myrinet, SCI, and QsNet, and prove that the way to design high performance NIC is feasible.
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References
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© 2005 Springer-Verlag Berlin Heidelberg
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Yang, X., Guo, L., Zhang, P., Sun, N. (2005). Design of System Area Network Interface Card Based on Intel IOP310. In: Wu, Z., Chen, C., Guo, M., Bu, J. (eds) Embedded Software and Systems. ICESS 2004. Lecture Notes in Computer Science, vol 3605. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11535409_23
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DOI: https://doi.org/10.1007/11535409_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28128-3
Online ISBN: 978-3-540-31823-1
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