High Performance Embedded Route Lookup Coprocessor for Network Processors

Abstract

Embedded Route Lookup Coprocessors (RLCs) are attractive for their potential in building high-performance Network Processors. But compared with conventional lookup schemes, it always imposes more severe restrictions on table size and power consumption, which poses challenge in the state of art. In this paper, we propose a novel lookup mechanism, Compounded CAM with Optimized Bitmap Compression (CCAM-OBC), which employs different lookup methods for prefixes of different length ranges, so as to combine the benefits of CAMs and bitmap compressed tries. With this scheme, table size, power consumption and update complexity are all well optimized while very high lookup throughput is achieved, which makes it a perfect solution to embedded RLC. For a real-life 130K-prefix route table, the implemented prototype performs more than 100 Million Packets Per Second (MPPS) with only 24KB TCAM, 48KB BCAM and 251KB SRAM. Furthermore, each update needs only 2 memory accesses averagely.

This work is supported by NSFC (No. 60173009 and 60373007), China 863 High-tech Plan (No. 2002AA103011-1 and 2003AA115110), China/Ireland Science and Technology Collaboration Research Fund (CI-2003-02) and the Specialized Research Fund for the Doctoral Program of Higher Education of China (No. 20040003048).