Abstract
A simulation-based comparison scheme for on-chip communication networks is presented. Performance of the network depends heavily on the application and therefore several test cases are required. In this paper, generic synthesizable 2-dimensional mesh and hierarchical bus, which is an extended version of a single bus, are benchmarked in a SoC context with five parameterizable test cases. The results show that the hierarchical bus offers a good performance and area trade-off. In the presented test cases, a 2-dimensional mesh offers a speedup of 1.1x – 3.3x over hierarchical bus, but the area overhead is of 2.3x – 3.4x, which is larger than performance improvement.
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Salminen, E., Kangas, T., Riihimäki, J., Lahtinen, V., Kuusilinna, K., Hämäläinen, T.D. (2005). Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_38
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DOI: https://doi.org/10.1007/11512622_38
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