Abstract
In this paper, we propose a power-aware branch logic for high performance embedded processors by filtering access to BTB and branch predictor. The proposed scheme reduces the energy consumed in BTB and branch predictor. For reducing the energy consumption in the BTB and the branch predictor, we present an aggressive hardware-based scheme that reduces the number of access to the BTB and the branch predictor. Moreover, compared with general branch logic, the proposed branch logic has no performance degradation. This scheme reduces the number of access to the BTB and the branch predictor by 21% – 50% and reduces the energy consumption in the BTB and the branch predictor by 15% – 41%.
This work was supported by the Brain Korea 21 Project.
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Shim, S., Kwak, J.W., Kim, C.H., Jhang, S.T., Jhon, C.S. (2005). Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_18
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DOI: https://doi.org/10.1007/11512622_18
Publisher Name: Springer, Berlin, Heidelberg
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