Requirements of Oxides as Gate Dielectricsfor CMOS Devices

Part of the Topics in Applied Physics book series (TAP, volume 106)


Analysis of fundamental material properties of the d-electron-based high-k dielectrics, which are under consideration for the application as gate dielectrics, indicates that this class of materials has serious limitations. However, the material intrinsic properties do not necessarily have to satisfy all performance requirements: certain properties can be modified by proper engineering. We formulate a technological approach to the requirements for gate dielectrics, which is specific to a given class of materials and aims to address negative aspects of intrinsic material properties.


71.55.-i; 72.80.Sk; 73.20.At; 75.47.Lx; 77.55.+f 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. A. M. Stoneham, J. L. Gavartin, A. L. Shluger: The oxide gate dielectrics: Do we know all we should?, J. Phys.: Condens. Matter 17, S2027 (2005) CrossRefGoogle Scholar
  2. International Technology Roadmap for Semiconductors (ITRS), 2003 Edition (Semiconductor Industry Association) URL: http/// Google Scholar
  3. G. Bersuker, P. Zeitzoff, G. Brown, H. R. Huff: Novel dielectric materials for future transistor generations, Mat. Today 6, 26 (2004) Google Scholar
  4. J. H. Sim, R. Choi, B. H. Lee, C. Young, P. Zeitzoff, D.-L. Kwong, G. Bersuker: Trapping/de-trapping gate bias dependence of -silicate dielectrics with poly and gate electrode, Jpn. J. Appl. Phys. 44, 2420 (2005) CrossRefGoogle Scholar
  5. C. Young, Y. Zhao, M. Pendley, B. H. Lee, K. Matthews, J. H. Sim, R. Choi, G. A. Brown, R. W. Murto, G. Bersuker: Ultra-short pulse current-voltage characterization of the intrinsic characteristics of high-k devices, Jpn. J. Appl. Phys. 44, 2437 (2005) CrossRefGoogle Scholar
  6. G. Bersuker, B. H. Lee, H. R. Huff, J. Gavartin, A. Shluger: Mechanism of charge trapping reduction in scaled high-k gate stacks, in E. Gusev (Ed.): Proc. NATO Workshop on Defects in Advanced High-k Dielectric Devices (Springer, Berlin, Heidelberg 2006) p. 227 CrossRefGoogle Scholar
  7. G. Lucovsky, C. C. Fulton, Y. Zhang, Y. Zou, J. Luning, L. F. Edge, J. L. Whitten, R. J. Nemanich, H. Ade, D. C. Schlom, V. V. Afanase'v, A. Stesmans, S. Zollner, D. Triyoso, B. R. Rogers: Conduction band-edge states associated with the removal of -state degeneracies by the Jahn–Teller effect, IEEE TDMR 5, 67 (2005) Google Scholar
  8. J. H. Sim, S. C. Song, P. D. Kirsch, C. D. Young, R. Choi, D. L. Kwong, B. H. Lee, G. Bersuker: Effects of ALD 2 thickness on charge trapping and mobility, Microelectronics Eng. 80, 218 (2005) CrossRefGoogle Scholar
  9. G. D. Wilk, D. A. Muller: Correlation of annealing effects on local electronic structure and macroscopic properties for 2 deposited by atomic layer deposition, Appl. Phys. Lett. 83, 3984 (2003) CrossRefGoogle Scholar
  10. G. Bersuker, P. Zeitzoff, J. H. Sim, B. H. Lee, R. Choi, G. Brown, C. D. Young: Mobility evaluation in transistors with charge trapping gate dielectrics, Appl. Phys. Lett. 87, 042905 (2005) CrossRefGoogle Scholar
  11. A. R. Brown, J. R. Watling, A. Asenov, G. Bersuker, P. Zeitzoff: Intrinsic parameter fluctuation in MOSFETs due to structural non-uniformity of high-k gate stack materials, SISPAD (2005) Abstract of SISPAD 2005 International Conference on simulation of semiconductor processes and devices, september 1–3 2005, Komaba Eminence, Tokyo, Japan Google Scholar
  12. F. Giustino, P. Umari, A. Pasquarello: Dielectric effect of a thin 2 interlayer at the interface between silicon and high-k oxides, Microelectron. Eng. 72, 299 (2004) CrossRefGoogle Scholar
  13. G. Bersuker, J. Peterson, J. Barnett, A. Korkin, J. H. Sim, R. Choi, B. H. Lee, J. Greer, P. Lysaght, H. R. Huff: Properties of the interfacial layer in the high-k gate stack and transistor performance, Electrochem. Soc. Proc. PV2005-05, 147 (2005) Google Scholar
  14. G. Bersuker, J. Gutt, N. Chaudhary, N. Moumen, B. H. Lee, J. Barnett, S. Gopalan, G. A. Brown, Y. Kim, C. D. Young, J. Peterson, H.-J. Li, P. M. Zeitzoff, J. H. Sim, P. Lysaght, M. Gardner, R. W. Murto, H. R. Huff: Integration issues of high-k gate stack: Process-induced charging, IEEE-IRPS Proc. 691, 479 (2004) Google Scholar

Authors and Affiliations

  1. 1.SEMATECHAustin, TexasUSA

Personalised recommendations