Charge Traps in High-k Dielectrics: Ab Initio Study of Defects in Pr-Based Materials
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In the nearest future, a dielectric with a dielectric constant k several times higher than that of SiO2 will be needed for the fabrication of CMOS (Complementary Metal-Oxide-Semiconductor) devices. Numerous metal oxides and silicates are investigated as candidates and various deposition and annealing techniques are being developed to improve the film quality. These techniques try to utilize the effects attributed to alloying, incorporation of nitrogen, gettering of oxygen, etc. At the same time, the basic knowledge on the microscopic properties of these materials needs improvement, particularly in the case of rare-earth oxides.
We present our fundamental understanding of point defects in Pr-based dielectrics (PrO1.5, PrO2, PrO1.75+delta, and PrSiO3.5) in the context of their influence on the electrical properties of the Metal Oxide Semiconductor (MOS) stack. From this point of view, there are three major issues associated with the presence of point defects: bulk charge traps, Trap Assisted Tunneling (TAT) centers, and electrically active interface states. The paper focuses on the first of these issues, as seen from the perspective of ab initio total energy calculations for atomic and electronic structures of point defects. We discuss the dependence of point defect formation on the chemical potential of oxygen and the role of impurities such as moisture, silicon, and boron. In particular, we derive a model of Si-related fixed charge and argue that this model is valid also for typical high-k dielectrics and for thermal SiO2/Si films.
Keywords71.55.-i; 72.80.Sk; 73.20.At; 75.47.Lx; 77.55.+f
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