Prototyping Execution Models for HTMT Petaflop Machine in Java

  • Lilia Yerosheva
  • Peter M. Kogge
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1602)


The Hybrid Technology MultiThreaded (HTMT) project is an attempt to design a machine with radically new hardware technologies that will scale to a petaflop by the 2004 time frame. These technologies range from multi-hundred GHz CPUs built from superconductive RSFQ devices through active optical networks and 3D holographic memories to Processing-In-Memory (PIM) for active memories. The resulting architecture resembles a three level hierarchy of “networks of processing nodes” of different technologies and functionality. All this new technology, however, has a huge and unknown effect on software execution models for applications. This paper discusses several potential HTMT models and how they can be prototyped and demonstrated using a combination of multithreaded Java and LAN-connected workstations.


Shared Memory Optical Network Execution Model Memory Hierarchy Tuple Space 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    ASCI. Accelerated Strategic Computing Initiative (1996),
  2. 2.
  3. 3.
    Kogge, P.M., Bass, S.C., Brockman, J.B., Chen, D.Z., Sha, E.: Pursuing a Petaflop: Point Designs for 100 TF Computers Using PIM Technologies. In: Frontiers 1996. 6th Symp. on Frontiers of Massively Parallel Computation, IEEE Comp. Society Press, Los Alamitos (1996)Google Scholar
  4. 4.
    Gao, G., Likharev, K., Messina, P., Sterling, T.: Hybrid Technology Multithreaded Architecture. In: 6th Symp. on Frontiers of Massively Parallel Computation, Annapolis, MD, pp. 98–105 (1996)Google Scholar
  5. 5.
    Kogge, P.M., Brockman, J.B., Sterling, T., Gao, G.: Processing In Memory: Chip to Petaflops. In: IRAM Workshop, Int. Symp. on Comp. Arch., Denver, CO (1997) (paper and presentation)Google Scholar
  6. 6.
    Moshovos, A., Breach, S.E., Vijaykumar, T.N., Sohi, G.S.: Dynamic speculation and synchronization of data dependences. In: Proceedings of the 24th Annual Int. Symp. on Comp. Arch., Denver, CO, pp. 181–193 (1997); ACM SIGARCH and IEEE Comp. Society, Comp. Arch. News (1997)Google Scholar
  7. 7.
    Gao, G.R., Theobald, K.B., Marquez, A., Strerling, T.: The HTMT Program Execution Model. CAPSL Technical Memo 09 (1997)Google Scholar
  8. 8.
    Lumetta, S.S., Culler, D.E.: Managing Concurrent Access for Shared Memory Active Messages, Comp. Science Division, Univ. of California at BerkeleyGoogle Scholar
  9. 9.
    Tucker, L.W., Mainwaring, A.: CMMD: Active Messages on the CM-5, Thinking Machines Corporation (1993)Google Scholar
  10. 10.
    T.: Active Messages: a Mechanism for Integrated Communication and Computation. In: 19th ISCA (1992)Google Scholar
  11. 11.
    Birrel, A., Nelson, B.J.: Implementing Remote Procedure Calls. ACM Transactions on Comp. Systems 2(1), 39–59 (1984)CrossRefGoogle Scholar
  12. 12.
    Almasi, G.S., Gottlieb, A.: Highly Parallel Computing, 2nd edn., pp. 253–255 (1994)Google Scholar
  13. 13.
    Kogge, P.M., Giambra, T., Sasnowitz, H.: RTAIS: An Embedded Parallel Processor for Real-time Decision Aiding. In: 1995 NAECON, Dayton, OH (1995)Google Scholar
  14. 14.
    Caromel, D., Vayssiere, J.: A Java Framework for Seamless Sequential, Multi-threaded, and Distributed Programming, In: Workshop on Java for High-Perf. Network. Stanford University, Palo Alto (1998)Google Scholar
  15. 15.
    Hirano, S., Yasu, Y., Igarashi, H.: Performance Evaluation of Popular Distributed Object Technologies for Java. In: Workshop on Java for High-Perf Network Computing. Stanford University, Palo Alto (1998)Google Scholar
  16. 16.
    Thiruvathukal, G.K., Thomas, L.S., Korczynski, A.T.: Reflective Remote Method Invocation. In: Workshop on Java for High-Perf Network computing. Stanford University, Palo Alto (1998)Google Scholar
  17. 17.
    Sterling, T.: Proceeding of the 1996 Petaflops Architecture Workshop, The Petaflops Systems Workshops, Caltech/JPL (1996)Google Scholar
  18. 18.
    Dongarra, J., Bunch, J., Moler, C., Stewart, G.W.: UNPACK User’s Guide. SIAM Publications, Philadelphia (1979)Google Scholar
  19. 19.
    Wijshoff, H.A.G.: Implementing Sparse BLAS Primitives on Concurrent/Vector Processors: a Case Study. Gibbons, A., Spirakis, P. (eds.) Lectures on parallel computation. Cambridge Int. Series on Parallel Computation, vol. 4. Cambridge university press, Cambridge (1993)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • Lilia Yerosheva
    • 1
  • Peter M. Kogge
    • 1
  1. 1.CSEUniversity of Notre DameNotre DameUSA

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