Abstract
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunication systems, make power management during test a critical problem. A Genetic Algorithm computes a set of redundant test sequences, then a genetic optimization algorithm selects the optimal subset of sequences able to reduce the consumed power, without reducing the fault coverage. Experimental results gathered on benchmark circuits show that our approach decreases the peak power consumption by 20% on the average with respect to the original test sequence generated ignoring the power dissipation problem, without affecting the fault coverage.
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© 1999 Springer-Verlag Berlin Heidelberg
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Corno, F., Rebaudengo, M., Sonza Reorda, M., Violante, M. (1999). Test Pattern Generation under Low Power Constraints. In: Poli, R., Voigt, HM., Cagnoni, S., Corne, D., Smith, G.D., Fogarty, T.C. (eds) Evolutionary Image Analysis, Signal Processing and Telecommunications. EvoWorkshops 1999. Lecture Notes in Computer Science, vol 1596. Springer, Berlin, Heidelberg. https://doi.org/10.1007/10704703_13
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DOI: https://doi.org/10.1007/10704703_13
Publisher Name: Springer, Berlin, Heidelberg
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