Test Program Generation from High-level Microprocessor Descriptions

  • E. Sánchez
  • M. Sonza Reorda
  • G. Squillero
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 17)

6.1 Abstract

This chapter describes and analyzes a methodology for gathering together test-programs for microprocessor cores during the complete design cycle starting from early design phases. The methodology is based on an almost automatic tool and could be applied to generate test-programs for stand-alone microprocessor cores as well as for these embedded in systems-on-chip. The main idea is to take advantage of all possible microprocessor descriptions delivered through the whole design cycle to generate test-programs able to achieve a high FC% at gate-level. Most of the efforts of the methodology presented are focused on test program generation from high-level microprocessor descriptions. A case study is presented tackling a pipelined microprocessor core.


Fault Coverage Device Under Test Code Coverage Verification Program Branch Coverage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag London Limited 2005

Authors and Affiliations

  • E. Sánchez
    • 1
  • M. Sonza Reorda
    • 1
  • G. Squillero
    • 1
  1. 1.Dipartimento di Automatica e InformaticaPolitecnico di TorinoTorinoItaly

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