6.1 Abstract
This chapter describes and analyzes a methodology for gathering together test-programs for microprocessor cores during the complete design cycle starting from early design phases. The methodology is based on an almost automatic tool and could be applied to generate test-programs for stand-alone microprocessor cores as well as for these embedded in systems-on-chip. The main idea is to take advantage of all possible microprocessor descriptions delivered through the whole design cycle to generate test-programs able to achieve a high FC% at gate-level. Most of the efforts of the methodology presented are focused on test program generation from high-level microprocessor descriptions. A case study is presented tackling a pipelined microprocessor core.
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Sánchez, E., Sonza Reorda, M., Squillero, G. (2005). Test Program Generation from High-level Microprocessor Descriptions. In: Sonza Reorda, M., Peng, Z., Violante, M. (eds) System-level Test and Validation of Hardware/Software Systems. Springer Series in Advanced Microelectronics, vol 17. Springer, London. https://doi.org/10.1007/1-84628-145-8_6
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DOI: https://doi.org/10.1007/1-84628-145-8_6
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