Test Generation: A Hierarchical Approach

  • G. Jervan
  • R. Ubar
  • Z. Peng
  • P. Eles
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 17)

5.1 Abstract

Advances in design tools and methods have led to an increasing amount of design activities being performed at higher levels of abstraction. Testability, on the other hand, is usually considered only when the detailed structural information of the design is available. This is mainly due to the lack of general applicability of the existing high-level test generation and design-for-test methods. In this chapter we will present an improvement of the classical hierarchical test generation approach by extending it to the higher levels of abstraction, while still considering the structural information from the lower levels. The approach proposed makes successful use of both high-level fault models and the classical gate-level fault models, and obtains results that are better than those obtained by a pure high-level test generator.


Test Generation Test Pattern Terminal Node Digital System Test Vector 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag London Limited 2005

Authors and Affiliations

  • G. Jervan
    • 1
    • 2
  • R. Ubar
    • 1
    • 2
  • Z. Peng
    • 1
    • 2
  • P. Eles
    • 1
    • 2
  1. 1.Linköping UniversityLinköpingSweden
  2. 2.Tallinn University of TechnologyTallinEstonia

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