4.1 Abstract
The adoption of the System-on-Chip design paradigm creates new challenges for designers and test engineers. In this chapter a high-level test generation approach is presented, which is able to produce high-quality vectors that can be fruitfully exploited for test and validation purposes of both the hardware and software components of System-on-Chip designs. Experimental results are reported showing that our high-level test generation algorithm produces high-quality vectors in terms of stuck-at fault coverage for hardware components and code mutants for software components. The vectors produced can also be exploited for validation purposes, as the results gathered while validating a processor core suggest.
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Goloubeva, O., Sonza Reorda, M., Violante, M. (2005). Test Generation: A Heuristic Approach. In: Sonza Reorda, M., Peng, Z., Violante, M. (eds) System-level Test and Validation of Hardware/Software Systems. Springer Series in Advanced Microelectronics, vol 17. Springer, London. https://doi.org/10.1007/1-84628-145-8_4
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DOI: https://doi.org/10.1007/1-84628-145-8_4
Publisher Name: Springer, London
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