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Modeling Permanent Faults

  • J. P. Teixeira
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Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 17)

2.1 Abstract

Test and validation of the hardware part of a hardware/software (HW/SW) system is a complex problem. Design for Testability (DfT), basically introduced at structural level, became mandatory to constrain design quality and costs. However, as product complexity increases, the test process (including test planning, DfT and test preparation) needs to be concurrently carried out with the design process, as early as possible during the top-down phase, starting from system-level descriptions. How can we, prior to the structural synthesis of the physical design, estimate and improve system testability, as well as perform test generation? The answer to this question starts with high-level modeling of permanent faults and its correlation with low-level defect modeling. Hence, this chapter addresses this problem, and presents some valuable solutions to guide high-quality test generation, based on high-level modeling of permanent faults.

Keywords

Test Pattern Test Vector Fault Coverage Fault Simulation Permanent Fault 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer-Verlag London Limited 2005

Authors and Affiliations

  • J. P. Teixeira
    • 1
  1. 1.IST / INESC-IDLisboaPortugal

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