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References

  1. S. Weber, “Part 1: Mobile Computing — Computer Design,” EE Times, Issue: 889, Feb 19, 1996.

    Google Scholar 

  2. F. Gardner, “Charge-pump phase-lock loops,” IEEE Transactions on Communications, vol. COM-28, pp. 1849–1858, Nov. 1980.

    Article  Google Scholar 

  3. D. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall Inc., Englewood Cliffs, New Jersey, 1991.

    Google Scholar 

  4. R. Best, Phase-locked Loops: Theory, Design, and Applications, New York, McGraw-Hill Inc., New York, 1993.

    Google Scholar 

  5. B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” J. of Solid-State Circuits, pp. 331–343, March 1996.

    Google Scholar 

  6. C. Vaucher, Architectures for RF Frequency Synthesizers, Boston: Kluwer Academic Publishers, 2002.

    Google Scholar 

  7. F. M. Gardner, Phase-Lock Techniques, New York: John Wiley & Sons, Inc. 1979.

    Google Scholar 

  8. O. Jacobs, Introduction to Control Theory, New York: Oxford University Press, 1993.

    Google Scholar 

  9. J. Hein and J. Scott, “z-Domain Model for Discrete-Time PLL’s,” IEEE Transactions on Circuits and Systems, vol. 35, no. 11, pp. 1393–1400, November 1988.

    Article  Google Scholar 

  10. A. Oppenheim and R. Schafer, Discrete-time Signal Processing, Englewood Cliffs, NJ: Prentice Hall, 1989.

    Google Scholar 

  11. A. M. Fahim and M. I. Elmasry, “A Fast Lock Digital Phase-Locked Loop Architecture for Wireless Applications,” IEEE Transactions on Circuits and Systems II, pp. 63–72, Feb. 2003.

    Google Scholar 

  12. D. Hess, “Cycle Slipping in a First-Order Phase-Locked Loop,” IEEE Transactions on Communication Technology, vol. Com-16, no. 2, pp. 255–260, April 1968.

    Article  Google Scholar 

  13. W. Egan, Frequency Synthesis by phase lock, Malabar, FL: R.E. Krieger Pub. Co., 1990.

    Google Scholar 

  14. M. Soyuer and R. Meyer, “Frequency Limitations of a Conventional Phase-Frequency Detector,” IEEE J. of Solid-State Circuits, vol. 25, no. 4, pp. 1019–1022, August 1990.

    Article  Google Scholar 

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© 2005 Kluwer Academic Publishers

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(2005). Phase-Locked Loop Fundamentals. In: Clock Generators for SOC Processors. Springer, Boston, MA. https://doi.org/10.1007/1-4020-8080-8_2

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  • DOI: https://doi.org/10.1007/1-4020-8080-8_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-8079-1

  • Online ISBN: 978-1-4020-8080-7

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