Abstract
Performance and power consumption of multi-processor Systems-on-Chip (SoCs) are increasingly determined by the scalability properties of the on-chip communication architecture. Networks-on-Chip (NoCs) are a promising solution for efficient interconnection of SoC components. This chapter focuses on low power NoC design techniques, analyzing the related issues at different layers of abstraction and providing examples taken from the most advanced NoC implementations presented in the open literature. Particular emphasis is given to application-specific NoC architectures, in that they represent the most promising scenario for minimization of communication-energy in multi-processor SoCs.
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Bertozzi, D., Benini, L., De Micheli, G. (2004). Energy-Efficient Network-On-Chip Design. In: Macii, E. (eds) Ultra Low-Power Electronics and Design. Springer, Boston, MA. https://doi.org/10.1007/1-4020-8076-X_12
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DOI: https://doi.org/10.1007/1-4020-8076-X_12
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