Abstract
Nano-computing in the form of quantum, molecular and other computing models is proliferating as we scale down to nano-meter fabrication technologies. According to many experts, it is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause lack of reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Various forms of redundancy such as NAND multiplexing, Triple Modular Redundancy (TMR), Cascaded Triple Modular Redundancy (CTMR) have been considered in the fault-tolerance literature. Also, redundancy has been applied at different levels of granularity, such as gate level, logic block level, logic function level, unit level etc. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome. In this chapter, we discuss different analytical and automation methodologies that can evaluate the reliability measures of combinational logic blocks, and can be used to analyze trade-offs between reliability and redundancy for different architectural configurations. We also illustrate the effectiveness of our reliability analysis tools pointing out certain anomalies which are counter intuitive and can be obtained easily by designers through automation, thereby providing better insight into defect-tolerant design decisions. We foresee that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points.
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Bhaduri, D., Shukla, S.K. (2004). Tools and Techniques for Evaluating Reliability Trade-Offs for Nano-Architectures. In: Shukla, S.K., Bahar, R.I. (eds) Nano, Quantum and Molecular Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-8068-9_6
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DOI: https://doi.org/10.1007/1-4020-8068-9_6
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