Summary
This chapter showed design, testing and implementation of a complete CPU. This design put all that we have covered in this book into one package. The design is complete and typical of any large system with a complex controller and data path. Use of the synthesizable subset of Verilog for development of a design for FPGA programming was shown. On the other hand, utilization of behavioral constructs of Verilog was demonstrated in developing a testbench for our processor.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer Science + Business Media, Inc.
About this chapter
Cite this chapter
Navabi, Z. (2005). Design of SAYEH Processor. In: Digital Design and Implementation with Field Programmable Devices. Springer, Boston, MA. https://doi.org/10.1007/1-4020-8012-3_14
Download citation
DOI: https://doi.org/10.1007/1-4020-8012-3_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-8011-1
Online ISBN: 978-1-4020-8012-8
eBook Packages: EngineeringEngineering (R0)