Abstract
The key design issues for ultralow-voltage (0.5–2 V) memory circuits are reviewed in terms of stable memory-cell operation, subthreshold current reduction, suppression of or compensation for design-parameter variations, and a single power supply and its standardization. The results obtained are as follows. (1) In DRAMs, coupled with high signal-to-noise-ratio memory-cell designs, the gate-source offset driving schemes suppress the cell-transistor subthreshold current increased by reduction of the threshold-voltage (VT). The gate-source self-backbiasing scheme drastically reduces the subthreshold current of the peripheral circuit, especially of iterative circuit blocks. Multi-VT and dynamic VT schemes recently proposed for logic LSI chips are also effective in reducing the subthreshold current. Various on-chip voltage generators and converters are becoming increasingly important in suppressing or compensating for the design parameter variations and in implementing and standardizing a single power supply. In SRAMs, a boosted power-supply scheme for the cell will eventually become necessary in order to accommodate the cell transistor’s high-VT needed to suppress a huge array subthreshold current. (2) SOI circuits are attractive in terms of ultralow-voltage operation although the floating body issue remains unsolved. Intrinsic fluctuations of FET parameters caused by random microscopic fluctuations in dopant atoms in an extremely short channel of 0.1 mm or so may limit ultralow-voltage operation, thus requiring new device designs.
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Itoh, K. (2004). Ultralow-Voltage Memory Circuits. In: Reis, R., Jess, J.A.G. (eds) Design of System on a Chip. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7929-X_7
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