Summary
In this chapter, we presented the models and representations used in this book. We first presented the layered graph intermediate representation used to capture the input description in Section 3.2. In Section 3.3, we discussed the additional information that is given as input with a design, such as the hardware resource library and the clock cycle period. We then presented the resource-constrained scheduling problem — without considering control flow — in Section 3.4. In Section 3.5, we introduced the modeling of the speculative and hierarchical code motions employed for scheduling control flow designs. We then extended the model for the scheduling problem to include control flow in Section 3.6. In this section, we also presented the modeling of resource utilization across mutually exclusive control paths in a design. The contributions of this chapter are the layered intermediate representation, the modeling for code motions across control flow and the formulation of the scheduling problem for designs with control flow.
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© 2004 Springer Science + Business Media, Inc.
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(2004). Models and Representations. In: SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7838-2_3
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DOI: https://doi.org/10.1007/1-4020-7838-2_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7837-8
Online ISBN: 978-1-4020-7838-5
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