Skip to main content
SpringerLink
Log in

Physical Design for System-On-A-Chip

  • Chapter
Essential Issues in SOC Design

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. L. C. Abel. On the ordering of connections for automatic wire routing. IEEE Transations on Computers, pages 1227-1233, November 1972.

    Google Scholar 

  2. S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa, and I. L. Markov. Unification of partitioning, placement and floorplanning. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 550-557, 2004.

    Google Scholar 

  3. S. N. Adya and I. L. Markov. Consistent placement of macroblock using floorplanning and standard-cell placement. In Proceedings of ACM International Symposium on Physical Design, pages 12-17, 2002.

    Google Scholar 

  4. S. N. Adya and I. L. Markov. Combinatorial techniques for mixed-size placement. ACM Transactions on Design Automation of Electronics Systems, 10(1):58-90, January 2005.

    Article  Google Scholar 

  5. S. N. Adya, I. L. Markov, and P. G. Villarrubia. On whitespace in mixed-size placement and physical synthesis. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 311-318, 2003.

    Google Scholar 

  6. S. B. Akers. A modification of Lee’s path connection algorithm. IEEE Transations on Electronic Computers, pages 97-98, February 1967.

    Google Scholar 

  7. C. J. Alpert and A. Devgan. Wire segmenting for improved buffer insertion. In Proceedings of ACM/IEEE Design Automation Conference, pages 588-593, June 1997.

    Google Scholar 

  8. K. Arrow, L. Huriwicz, and H. Uzawa. Studies in Nonlinear Programming. Stanford University Press, Stanford, Calif, 1958.

    Google Scholar 

  9. H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.

    Google Scholar 

  10. G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske, and J. S. Zhang. Substrate noise modeling in early floorplanning of mixed-signal SOCs. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 819-823, 2005.

    Google Scholar 

  11. M. Burstein and R. Pelavin. Hierarchical wire routing. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, CAD-2(4):223-234, October 1983.

    Article  Google Scholar 

  12. M. Burstein and M. N. Youssef. Timing influenced layout design. In Proceedings of ACM/IEEE Design Automation Conference, pages 124-130, 1985.

    Google Scholar 

  13. A. Caldwell, A. Kahng, and I. Markov. Can recursive bisection alone produce routable placement? In Proceedings of ACM/IEEE Design Automation Conference, 2000.

    Google Scholar 

  14. H. H. Chan, S. N. Adya, and I. L. Markov. Are floorplan representations important in digital design? In Proceedings of ACM International Symposium on Physical Design, pages 129-136, 2005.

    Google Scholar 

  15. T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proceedings of ACM International Symposium on Physical Design, pages 185-192, 2005.

    Google Scholar 

  16. C.-C. Chang, J. Cong, and X. Yuan. Multi-level placement for large-scale mixed-size ic designs. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 325-330, 2003.

    Google Scholar 

  17. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu. B*-trees: A new representation for non-slicing floorplans. In Proceedings of ACM/IEEE Design Automation Conference, pages 458-463, 2000.

    Google Scholar 

  18. Y.-W. Chang and S.-P. Lin. MR: A new framework for multilevel full-chip routing. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 23(5):793-800, May 2004.

    Article  Google Scholar 

  19. Y.-W. Chang, K. Zhu, and D.-F. Wong. Timing-driven routing for symmetrical-array-based fpgas. ACM Transactions on Design Automation of Electronics Systems, 5(3):433-450, July 2000.

    Article  Google Scholar 

  20. H. Chen, C.-K. Cheng, A. B. Kahng, M. Mori, and Q. Wang. Optimal planning for mesh-based power distribution. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 444-449, 2004.

    Google Scholar 

  21. T.-C. Chen and Y.-W. Chang. IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, 2005.

    Google Scholar 

  22. T.-C. Chen and Y.-W. Chang. Modern floorplanning based on fast simulated annealing. In Proceedings of ACM International Symposium on Physical Design, pages 104-112, 2005.

    Google Scholar 

  23. T.-C. Chen and Y.-W. Chang. Multilevel gridless routing considering optical proximity correction. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 1160-1163, January 2005.

    Google Scholar 

  24. T.-C. Chen, Y.-W. Chang, and S.-C. Lin. A novel framework for multilevel full-chip gridless routing. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, January 2006.

    Google Scholar 

  25. T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y.-W. Chang. NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. In Proceedings of ACM International Symposium on Physical Design, pages 236-238, 2005.

    Google Scholar 

  26. Y.-H. Cheng and Y.-W. Chang. Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. In aspdac, pages 624-627, Piscataway, NJ, USA, 2004. IEEE Press.

    Google Scholar 

  27. M. Cho, H. Shin, and D. Z. Pan. Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal socs. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, January 2006.

    Google Scholar 

  28. S. Chowdhury. Optimum design of reliable ic power networks having general graph topologies. In Proceedings of ACM/IEEE Design Automation Conference, pages 787-790, 1989.

    Google Scholar 

  29. J. Cong, J. Fang, M. Xie, and Y. Zhang. MARS-a multilevel full-chip gridless routing system. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 24(3):382-394, March 2005.

    Article  Google Scholar 

  30. J. Cong, J. Fang, and Y. Zhang. Multilevel approach to full-chip gridless routing. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 396-403, 2001.

    Google Scholar 

  31. J. Cong, L. He, K.-Y. Khoo, C.-K. Koh, and Z. Pan. Interconnect design for deep submicron ICs. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 478-485, 1997.

    Google Scholar 

  32. J. Cong, T. Kong, and D. Z. Pan. Buffer Block Planning for Interconnect-Driven Floorplanning. Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 358-363, 1999.

    Google Scholar 

  33. J. Cong and P. H. Madden. Performance driven global routing for standard cell design. In Proceedings of ACM International Symposium on Physical Design, pages 73-80, April 1997.

    Google Scholar 

  34. J. Cong, M. Romesis, and J. R. Shinnerl. Fast floorplanning by look-ahead enabled recursive bipartitioning. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, 2005.

    Google Scholar 

  35. J. Cong, M. Xie, and Y. Zhang. An enhanced multilevel routing system. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 51-58, November 2002.

    Google Scholar 

  36. T. Cormen, C. Leiserson, R. Rivest, and C. Stein. Introduction to Algorithms. The MIT Press/McGraw-Hill Book Company, 2nd edition, 2001.

    Google Scholar 

  37. A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu, and D. Bearden. Design and analysis of power distribution networks in powerpc microprocessors. In Proceedings of ACM/IEEE Design Automation Conference, pages 738-743, 1998.

    Google Scholar 

  38. K. Doll, F. M. Johannes, and K. J. Antreich. Iterative placement improvement by network flow methods. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 13(10):1189-1200, 1994.

    Article  Google Scholar 

  39. F. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu, and A. Zelikovsky. Provably good global buffering by multi-terminal multicommodity flow approximation. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 120-125, New York, NY, USA, 2001. ACM Press.

    Google Scholar 

  40. A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Jukl, P. Kozak, and M. Wiesel. Chip layout optimization using critical path weighting. In Proceedings of ACM/IEEE Design Automation Conference, pages 133-136, 1984.

    Google Scholar 

  41. A. E. Dunlop and B. Kernighan. A procedure for placement of standard-cell VLSI circuits. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, CAD-4, January 1985.

    Google Scholar 

  42. H. Eisenmann and F. M. Johannes. Generic global placement and floorplanning. In Proceedings of ACM/IEEE Design Automation Conference, pages 269-274, 1998.

    Google Scholar 

  43. W. C. Elmore. The transient response of damped linear networks with particular regard to wide-band amplifiers. Journal of Applied Physics, 19(1):55-63, Jan. 1948.

    Article  Google Scholar 

  44. W. N. et al. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. In US Patent 6301693, October 2001.

    Google Scholar 

  45. L. C. Evans. Partial Diferential Equations. American Mathematical Society, Providence, 2002.

    Google Scholar 

  46. C. M. Fidducia and R. M. Mattheyses. A linear-time heuristic for improving network partitions. In Proceedings of ACM/IEEE Design Automation Conference, pages 175-181, 1982.

    Google Scholar 

  47. G. H. Golub and V. L. C. F. Matrix Computations. Johns Hopkins University Press, 1996.

    Google Scholar 

  48. P.-N. Guo, C.-K. Cheng, and T. Yoshimura. An O-tree representation of non-slicing floorplan and its applications. In Proceedings of ACM/IEEE Design Automation Conference, pages 268-273, 1999.

    Google Scholar 

  49. F. O. Hadlock. A shortest path algorithm for grid graphs. Networks, pages 323-334, 1977.

    Google Scholar 

  50. T. Hamada, C. K. Cheng, and P. M. Chau. Prime: A placement tool using a piece wise linear resistive network approach. In Proceedings of ACM/IEEE Design Automation Conference, pages 531-536, 1993.

    Google Scholar 

  51. M. Hayashi and S. Tsukiyama. A hybrid hierarchical approach for multi-layer global routing. In Proceedings of European Design and Test Conference, pages 492-496, 1995.

    Google Scholar 

  52. D. Hightower. A solution to line routing problems on the continuous plane. In Proceedings of Design Automation Workshop, pages 1-24, 1969.

    Google Scholar 

  53. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen. Multilevel full-chip routing for the x-based architecture. In Proceedings of ACM/IEEE Design Automation Conference, pages 597-602, June 2005.

    Google Scholar 

  54. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen. Multilevel routing with antenna avoidance. In Proceedings of ACM International Symposium on Physical Design, pages 34-40, April 2004.

    Google Scholar 

  55. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D.-T. Lee. A fast crosstalk- and performance-driven multilevel routing system. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 382-387, November 2003.

    Google Scholar 

  56. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D.-T. Lee. Crosstalk- and performance-driven multilevel full-chip routing. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 24(6):869-878, 2005.

    Article  Google Scholar 

  57. T. C. Hu and M.-T. Shing. A decomposition algorithm for circuit routing. In VLSI Circuit Layout: Theory and Design, pages 144-152. IEEE Press, New York, NY, 1985.

    Google Scholar 

  58. M. Jackson and E. S. Kuh. Performance-driven placement of cell based IC’s. In Proceedings of ACM/IEEE Design Automation Conference, pages 370-375, 1989.

    Google Scholar 

  59. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao. Simultaneous Floorplanning and Buffer Block Planning. Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 431-434, 2003.

    Google Scholar 

  60. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao. Simultaneous Floorplan and Buffer Block Optimization. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 23(5):694-703, 2004.

    Article  Google Scholar 

  61. Z.-W. Jiang, T.-C. Chen, T.-C. Hsu, H.-C. Hsu, and Y.-W. Chang. NTUplace2: a hybrid placement tool using partitioning and analytical techniques. In Proceedings of ACM International Symposium on Physical Design.

    Google Scholar 

  62. A. B. Kahng, I. Markov, and S. Reda. On legalization of row-based placements. In Proceedings of ACM Great Lakes Symposium on VLSI, pages 214-219, 2004.

    Google Scholar 

  63. A. B. Kahng and S. Reda. Placement feedback: a concept and method for better min-cut placements. In Proceedings of ACM/IEEE Design Automation Conference, pages 357-362, 2004.

    Google Scholar 

  64. A. B. Kahng, S. Reda, and Q. Wang. Architecture and details of a high quality, large-scale analytical placer. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 890-897, 2005.

    Google Scholar 

  65. A. B. Kahng, P. Tucker, and A. Zelikovsky. Optimization of linear placements for wirelength minimization with free sites. In Proceedings of IEEE/ACM Asia South Pacific Design Automation Conference, pages 241-244, 1999.

    Google Scholar 

  66. A. B. Kahng and Q. Wang. An analytic placer for mixed-size placement and timing-driven placement. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 565-572, 2004.

    Google Scholar 

  67. A. B. Kahng and Q. Wang. An analytic placer for mixed-size placement and timing-driven placement. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 565-572, 2004.

    Google Scholar 

  68. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Application in vlsi domain. In Proceedings of ACM/IEEE Design Automation Conference, page 526-529, 1997.

    Google Scholar 

  69. R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh. Pattern routing: Use and theory for increasing predictability and avoiding coupling. In IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, pages 777-790, November 2002.

    Google Scholar 

  70. A. Khatkhate, C. Li, A. R. Agnihotri, M. C. Yildiz, S. Ono, C.-K. Koh, and P. H. Madden. Recursive bisection based mixed block placement. In Proceedings of ACM International Symposium on Physical Design, pages 84-89, 2004.

    Google Scholar 

  71. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(4598):671-680, 1983.

    Article  MathSciNet  Google Scholar 

  72. J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich. Gordian: Vlsi placement by quadratic programming and slicing optimization. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 10.

    Google Scholar 

  73. T. Kong. A novel net weighting algorithm for timing-driven placement. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 172-176, 2002.

    Google Scholar 

  74. D. Kouroussis and F. N. Najm. A static pattern-independent technique for power grid voltage integrity verification. In Proceedings of ACM/IEEE Design Automation Conference, pages 99-104, 2003.

    Google Scholar 

  75. C. Y. Lee. An algorithm for path connection and its application. IRE Transactions on Electronic Computer, EC-10, pages 346-365, 1961.

    Google Scholar 

  76. H.-C. Lee, J.-M. Hsu, Y.-W. Chang, and H. Yang. Multilevel floorplanning/placement for large-scale modules using b*-trees. In Proceedings of ACM/IEEE Design Automation Conference, 2003.

    Google Scholar 

  77. K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C.-C. Su, and J. E. Chen. Multilevel full-chip routing with testability and yield enhancement. In Proceedings of System Level Interconnect Prediction Workshop, pages 236-238, April 2005.

    Google Scholar 

  78. S. Lin and N. Chang. Challenges in power-ground integrity. In Proceedings of IEEE International Conference on Computer Design, pages 651-654, 2001.

    Google Scholar 

  79. S.-P. Lin and Y.-W. Chang. A novel framework for multilevel routing considering routability and performance. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 44-50, November 2002.

    Google Scholar 

  80. Y.-L. Lin, Y.-C. Hsu, and F.-S. Tsai. Hybrid routing. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 9(2):151-157, February 1990.

    Article  Google Scholar 

  81. V. Litovski and M. Zwolinski. VLSI Circuit Simulation and Optimization. Chapman & Hall, 1997.

    Google Scholar 

  82. C.-W. Liu and Y.-W. Chang. Floorplan and power/ground network co-synthesis for fast design convergence. In Proceedings of ACM International Symposium on Physical Design, 2006.

    Google Scholar 

  83. M. Marek-Sadowska. Global router for gate array. In Proceedings of IEEE International Conference on Computer Design, pages 332-337, October 1984.

    Google Scholar 

  84. M. Marek-Sadowska. Route planner for custom chip design. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 246-249, November 1986.

    Google Scholar 

  85. R. McInerney, M. Page, K. Leeper, T. Hillie, H. Chan, and B. Basaran. Methodology for repeater insertion management in the RTL, layout, floorplan, and fullchip timing databases of the Itanium microprocessor. In Proceedings of ACM International Symposium on Physical Design, pages 99-104, 2000.

    Google Scholar 

  86. K. Mikami and K. Tabuchi. A computer program for optimal routing of printed circuit connectors. In Proceedings of IFIP, pages 1475-1478, November 1968.

    Google Scholar 

  87. K. W. Morton and D. F. Mayers. Numerical Solution of Partial Differential Equations. Cambridge University Press, 1994.

    Google Scholar 

  88. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajatani. Rectangle-packing based module placement. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 472-479, 1995.

    Google Scholar 

  89. R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa. Generation of performance constraints for layout. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 8:860-874, August 1989.

    Google Scholar 

  90. B. Owens, S. Alduri, P. Birrer, R. Shreeve, S. K. Arunachalam, and K. Mayaram. Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE Journal of Solid-State Circuits, 40, February 2005.

    Google Scholar 

  91. P. Raghavan and C. D. Thompson. Randomized rounding: A technique for provably good algorithms and algorithmic proofs. In Proceedings of Combinatorica, pages 365-374, 1987.

    Google Scholar 

  92. S. M. Sait and H. Youssef. VLSI Physical Design Automation: Theory and Practice. World Scientific Publishers, Singapore, 1999.

    Google Scholar 

  93. P. Sarkar, V. Sundararaman, and C.-K. Koh. Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning. Proceedings of ACM International Symposium on Physical Design, pages 186-191, 2000.

    Google Scholar 

  94. M. Sarrafzadeh, D. A. Knol, and G. E. Tellez. A delay budgeting algorithm ensuring maximum flexibility in placement. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 16:1332-1341, November 1997.

    Article  Google Scholar 

  95. P. Saxena, N. M. P. Cocchini, and D. Kirkpatrick. Repeater scaling and its impact on cad. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 23(4):451 - 463, 2004.

    Article  Google Scholar 

  96. C. Sechen and A. Sangiovanni-Vincentelli. The timberwolf placement and routing package. IEEE Journal of Solid-State Circuits, 20.

    Google Scholar 

  97. J. Singh and S. S. Sapatnekar. Topology optimization of structured power/ground networks. In Proceedings of ACM International Symposium on Physical Design, pages 116-123, 2004.

    Google Scholar 

  98. J. Soukup. Fast maze router. In Proceedings of ACM/IEEE Design Automation Conference, pages 100-102, June 1978.

    Google Scholar 

  99. A. Srinivasan, K. Chaudhary, and E. S. Kuh. RITUAL: A performance driven placement for small-cell IC’s. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 48-51, 1991.

    Google Scholar 

  100. W. Swartz and C. Sechen. Timing driven placement for large standard cell circuits. In Proceedings of ACM/IEEE Design Automation Conference, pages 211-215, 1995.

    Google Scholar 

  101. T. Taghavi, X. Yang, and B.-K. Choi. Dragon2005: Large-scale mixed-size placement tool. In Proceedings of ACM International Symposium on Physical Design, pages 245-247, 2005.

    Google Scholar 

  102. X. Tang, R. Tian, and D. F. Wong. Fast evaluation of sequence pair in block placement by longest common subsequence computation. IEEE Transations on Computer-Aided Design of Integrated Circuits and Systems, 20(12):1406-202, 2001.

    Article  Google Scholar 

  103. X. Tang and D. F. Wong. Planning Buffer Locations by Network Flows. Proceedings of ACM International Symposium on Physical Design, pages 180-185, 2000.

    Google Scholar 

  104. K. Wang and M. Marek-Sadowska. On-chip power supply network optimization using multigrid-based technique. In Proceedings of ACM/IEEE Design Automation Conference, pages 113-118, 2003.

    Google Scholar 

  105. S.-W. Wu and Y.-W. Chang. Efficient power/ground network analysis for power integrity-driven design methodology. In Proceedings of ACM/IEEE Design Automation Conference, pages 177-180, 2004.

    Google Scholar 

  106. H. Xiang, X. Tang, and M. D. F. Wong. Bus-driven floorplanning. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, pages 66-73, 2003.

    Google Scholar 

  107. X. Yang, B. K. Choi, and M. Sarrafzadeh. Timing-driven placement using design hierarchy guided constraint generation. In Proceedings of IEEE/ACM International Conference on Computer Aided Design, 2002.

    Google Scholar 

  108. B. Yao, H. Chen, C.-K. Cheng, N.-C. Chou, L.-T. Liu, and P. Suaris. Unified quadratic programming approach for mixed mode placement. In Proceedings of ACM International Symposium on Physical Design, pages 193-199, 2005.

    Google Scholar 

  109. M. Yildiz and P. Madden. Global objectives for standard cell placement. In Proceedings of ACM Great Lakes Symposium on VLSI, pages 68-72, 2001.

    Google Scholar 

  110. M. Yildiz and P. Madden. Improved cut sequences for partitioning-based placement. In Proceedings of ACM/IEEE Design Automation Conference, pages 776-779, 2001.

    Google Scholar 

  111. J.-S. Yim, S.-O. Bae, and C.-M. Kyung. A floorplan-based planning methodology for power and clock distribution in asics. In Proceedings of ACM/IEEE Design Automation Conference, pages 766-771, 1999.

    Google Scholar 

  112. H. Youssef, R. Lin, and E. Shragowitz. Bounds on net delays for VLSI circuits. IEEE Transactions on Circuits and Systems, 39:815-824, November 1992.

    MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan

    Yao-Wen Chang

  2. Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan

    Tung-Chieh Chen & Huang-Yu Chen

Authors
  1. Yao-Wen Chang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Tung-Chieh Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Huang-Yu Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. National Tsing Hua University, Taiwan

    Youn-Long Steve Lin

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer

About this chapter

Cite this chapter

Chang, YW., Chen, TC., Chen, HY. (2006). Physical Design for System-On-A-Chip. In: Lin, YL.S. (eds) Essential Issues in SOC Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-5352-5_9

Download citation

  • DOI: https://doi.org/10.1007/1-4020-5352-5_9

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-1-4020-5351-1

  • Online ISBN: 978-1-4020-5352-8

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation