# INTRODUCTION TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN

## **Abstract**

Up to now the evolution of digital microelectronics is characterized by the exponential growth of the number of transistors per chip which results in an exponential increase of computing power. In 1965 Gordon Moore noted that the number of transistors per chip will double every 18 to 24 month. This famous prediction which is known as Moore’s Law has become a self fulfilling prophecy which is not limited to the transistor count anymore: Moreover, most characteristic technology or system figures show an exponential progression. Fig. 1.1 for instance shows the evolution of the computing power in million instructions per second (MIPS) of the Intel microprocessors [Moore, 2003]. It is amazing that the postulated exponential growth is realized almost perfectly. However, as shown in Fig. 1.2 this performance increase is achieved only with an exponential growth of the transistor number per chip. The continuous growth of the device number is enabled by technology scaling which results in a higher transistor density but also in an increased die size. Indeed even the die size has been doubled every ten years. Technology scaling, i.e. the shrinking of the transistor dimensions not only increases the gate density but also increases the switching speed of logic gates. This reflects in continuously growing clock frequencies. As the price of most chips is constant over the particular product generations the exponential growth of the device number corresponds to an exponential decay of the cost per transistor or basic logic function respectively. The positive aspects of Moore’s Laware accompanied by a couple of drawbacks which also show an exponential behavior: More computing power and more transistors means also more internal capacitance, more switching events and consequently more power dissipation.

## Keywords

Threshold Voltage Power Dissipation Short Channel Effect Circuit Block Clock Tree## Preview

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