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Troyanovsky, B., O'Halloran, P., Mierzwinski, M. (2006). Compact modeling in Verilog-A. In: GRABINSKI, W., NAUWELAERS, B., SCHREURS, D. (eds) TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN. Springer, Dordrecht. https://doi.org/10.1007/1-4020-4556-5_10
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