Abstract
This paper presents a codesign environment for the UltraSONIC reconfigurable computing platform which is designed specifically for real-time video applications. A codesign environment with automatic partitioning and scheduling between a host processor and a number of reconfigurable coprocessors is described. A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our system is demonstrated with an FFT application.
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References
R. Ernst “Codesign of embedded systems: status and trends”, IEEE Design & Test of Computers, 1998.
G. Manikutty, and H. Hanson, “Hardware/Software Partitioning of Synchronous Dataflow Graphs in the ACS domain of Ptolemy”, University of Texas, Literature Survey, Final Report May 12 1999.
M. Hall, P. Diniz, K. Bondalapati, H. Ziegler et al., “DEFACTO: A Design Environment for Adaptive Computing Technology”, Proceedings of the 6th Reconfigurable Architectures Workshop, 1999.
O. Mencer, M. Morf, and M. J. Flynn, “PAM-Blox: high performance FPGA design for adaptive computing”, FPGAs for Custom Computing Machines, 1998.
P. H. Chou, R. B. Ortega, and G. Borriello, “The Chinook hardware/software co-synthesis system”, System Synthesis, 1995.
P. Coste, F. Hessel, P. Le Marrec, Z. Sugar et al., “Multilanguage design of heterogeneous systems”, Hardware/Software Codesign, 1999.
J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel et al., “Design Exploration in CASTLE”, Workshop on High Level Synthesis Algorithms Tools and Design (HILES), 1995.
R. Ernst, “Hardware/Software Co-Design of Embedded Systems”, Asia Pacific Conference on Computer Hardware Description Languages, 1997.
T. Pop, P. Eles, and Z. Peng, “Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems”, Hardware/Softwarw Codesign, 2002.
V. Srinivasan, S. Govindarajan, and R. Vemuri, “Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, pp. 140–158, 2001.
J. Hou, and W. Wolf, “Process partitioning for distributed embedded systems”, Hardware/Software Co-Design, 1996.
T. Wiangtong, P. Y. K. Cheung, and W. Luk, “Comparing Three Heuristic Search Methods for Functional Partitioning in HW-SW Codesign”, International Journal on Design Automation for Embedded Systems, vol. 6, pp. 425–449, July 2002.
S. D. Haynes et al., “UltraSONIC: A Reconfigurable Architecture for Video Image Processing”, Field-Programmable Logic and Applications (FPL), 2002.
T. Wiangtong, P. Y. K. Cheung, and W. Luk, “Cluster-Driven Hardware/Software Partitioning and Scheduling Approach For a Reconfigurable Computer System”, Field-Programmable Logic and Applications (FPL), 2003.
G. D. Micheli, “Computer-aided hardware-software codesign”, IEEE Micro, Vol 14, pp. 10–16, 1994.
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Wiangtong, T., Cheung, P.Y., Luk, W. (2005). A Unified Codesign Environment. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_7
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DOI: https://doi.org/10.1007/1-4020-3128-9_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3127-4
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