Abstract
This chapter describes the structures and principles of stream-based, reconfigurable XPP Architectures from PACTXPP Technologies AG (Munich, Germany). The status of an adaptive System-on-Chip (SoC) integration is given, consisting of a SPARC-compatible LEON processor-core, a coarse-grain XPP-array of suitable size, and efficient multi-layer Amba-based communication interfaces. In addition PACTs newest XPP architectures are described, realizing a new runtime reconfigurable data processing technology that replaces the concept of instruction sequencing by configuration sequencing with high performance application areas envisioned from embedded signal processing to co-processing in different DSP-like and mobile application environments. The underlying programming model is motivated by the fact, that future oriented applications need to process streams of data decomposed into smaller sequences which are processed in parallel. Finally, first-time-right commercial chip synthesis were performed successfully onto 0.13 µm STMicro CMOS technology.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
R. W. Hartenstein, J. Becker et al.: A Novel Machine Paradigm to Accelerate Scientific Computing; Special issue on Scientific Computing of Computer Science and Informatics Journal, Computer Society of India, 1996.
J. Becker, T. Pionteck, C. Habermann, M. Glesner: Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture; in: Proc. of IEEE Computer Society Annual Workshop on VLSI (WVLSI 2001), Orlando, Florida, USA, April 19–20, 2001.
J. Becker (Invited Tutorial): Configurable Systems-on-Chip (CSoC); in: Proc. of 9th Proc. of XV Brazilian Symposium on Integrated Circuit Design (SBCCI 2002), Porto Alegre, Brazil, September 5–9, 2002.
Xilinx Corp.: http://www.xilinx.com/products/virtex.htm.
Altera Corp.: http://www.altera.com
Triscend Inc.: http://www.triscend.com
Triscend A7 Configurable System-on-Chip Platform—Data Sheet http://www.triscend.com/products/dsa7csoc_summary.pdf
LucentWeb http://www.lucent.com/micro/fpga/
PACT Corporation: http://www.pactcorp.com
The XPP Communication System, PACT Corporation, Technical Report 15, 2000.
V. Baumgarte, F. Mayr, A. Nückel, M. Vorbach, M. Weinhardt: PACT XPP—A Self-Reconfigurable Data Processing Architecture; The 1st Intl. Conference of Engineering of Reconfigurable Systems and Algorithms (ERSA01), Las Vegas, NV, June 2001.
Hitachi Semiconductor: http://semiconductor.hitachi.com/news/triscend.html
Peter Jung, Joerg Plechinger.: M-GOLD: a multimode basband platform for future mobile terminals, CTMC'99, IEEE International Conference on Communications, Vancouver, June 1999.
Jan M. Rabaey: System Design at Universities: Experiences and Challenges; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE99), July 19–21, Arlington VA, USA.
S. Copen Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, R. Laufer: PipeRench: a Coprocessor for Streaming Multimedia Acceleration in ISCA 1999. http://www.ece.cmu.edu/research/piperench/
MIT Reinventing Computing: http://www.ai.mit.edu/projects/transit dpga_prototype_documents.html
N. Bagherzadeh, F. J. Kurdahi, H. Singh, G. Lu, M. Lee: Design and Implementation of the MorphoSys Reconfigurable Computing Processor; J. of VLSI and Signal Processing-Systems for Signal, Image and Video Technology, 3/2000.
Hui Zhang, Vandana Prabhu, Varghese George, Marlene Wan, Martin Benes, Arthur Abnous, A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications, Proc. of ISSCC2000.
Pleiades Group: http://bwrc.eecs.berkeley.edu/Research/Configurable_Architectures/
R. Hartenstein, R. Kress, and H. Reinig A new FPGA architecture for word-oriented datapaths In Proc. FPL'94, Prague, Czech Republic, September 1994. Springer LNCS 849.
E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, and P. Finch: Baring it all to software: Raw machines IEEE Computer, pages 86–93, September 1997. [22] ARM Corp.: http://www.arm.com/arm/AMBA
J. Becker, M. Vorbach: Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC); IEEE Computer Society Annual Workshop on VLSI (WVLSI 2003), Tampa, Florida, USA, February, 2003.
J. Becker, A. Thomas, M. Vorbach, V. Baumgarte: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-grain XPP-/Leon-based Architecture Integration; Design, Automation and Test in Europe Conference (DATE 2003), Munich, March 2003.
M. Vorbach, J. Becker: Reconfigurable Processor Architectures for Mobile Phones; Reconfigurable Architectures Workshop (RAW 2003), Nice, France, April, 2003.
Jiri Gaisler: The LEON Processor User's Manual, http://www.gaisler.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer
About this chapter
Cite this chapter
Becker, J., Vorbach, M. (2005). Stream-based XPP Architectures in Adaptive System-on-Chip Integration. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_3
Download citation
DOI: https://doi.org/10.1007/1-4020-3128-9_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3127-4
Online ISBN: 978-1-4020-3128-1
eBook Packages: EngineeringEngineering (R0)