Abstract
In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this paper proposes a new arithmetic unit (AU) in GF(2m) for reconfigurable hardware implementation such as FPGAs. The proposed AU performs both division and multiplication in GF(2m). These operations are at the heart of elliptic curve cryptosystems (ECC). Analysis shows that the proposed AU has significantly less area complexity and has roughly the same or lower latency compared with some related circuits. In addition, we show that the proposed architecture preserves a high clock rate for large m (up to 571), when it is implemented on Altera’s EP2A70F1508C-7 FPGA device. Furthermore, since the new architecture does not restrict the choice of irreducible polynomials and has the features of regularity, modularity, and unidirectional data flow, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed architecture is well suited for implementing both the division and multiplication units of ECC on FPGAs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
IEEE P1363, Standard Specifications for Publickey Cryptography, 2000.
A. Menezes, Elliptic Curve Public Key Cryptosystems, Kluwer Academic Publishers, 1993.
I. F. Blake, G. Seroussi, and N. P. Smart, Elliptic Curves in Cryptography, Cambridge University Press, 1999.
D. Hankerson, J. L. Hernandez, and A. Menezes, “Implementation of Elliptic Curve Cryptography Over Binary Fields,” CHES 2000, LNCS 1965, Springer-Verlag, 2000.
D. Bailey and C. Paar, “Efficient Arithmetic in Finite Field Extensions with Application in Elliptic Curve Cryptography,” J. of Cryptology, vol. 14, no. 3, pp. 153–176, 2001.
L. Gao, S. Shrivastava and G. E. Solbelman, “Elliptic Curve Scalar Multiplier Design Using FPGAs,” CHES 2000, LNCS 1717, Springer-Verlag, 1999.
G. Orlando and C. Parr, “A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m),” CHES 2000, LNCS 1965, Springer-Verlag, 2000.
M. Bednara, M. Daldrup, J. von zur Gathen, J. Shokrollahi, and J. Teich, “Reconfigurable Implementation of Elliptic Curve Crypto Algorithms,” Proc. of the International Parallel and Distributed Processing Symposium (IPDPS'02), pp. 157–164, 2002.
G. B. Agnew, R. C. Mullin, and S. A. Vanstone, “An Implementation for Elliptic Curve Cryptosystems Over F 1552 ,” IEEE J. Selected Areas in Comm., vol. 11, no. 5, pp. 804–813, June 1993.
M.A. Hasan and A.G. Wassal, “VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor”, IEEE Trans. Computers, vol. 49, no. 10, pp. 1064–1073, Oct. 2000.
C.-L. Wang and J.-L. Lin, “A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2m),” IEEE Trans. Computers., vol. 42, no. 9, pp. 1141–1146, Sep. 1993.
M.A. Hasan and V.K. Bhargava, “Bit-Level Systolic Divider and Multiplier for Finite Fields GF(2m),” IEEE Trans. Computers, vol. 41, no. 8, pp. 972–980, Aug. 1992.
J.-H. Guo and C.-L. Wang, “Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF(2m),” IEEE Trans. Computers., vol. 47, no. 10, pp. 1161–1167, Oct. 1998.
J.R. Goodman, “Energy Scalable Reconfigurable Cryptographic Hardware for Portable Applications,” PhD thesis, MIT, 2000.
J.-H. Guo and C.-L. Wang, “Bit-serial Systolic Array Implementation of Euclid's Algorithm for Inversion and Division in GF(2m)”, Proc. 1997 Int. Symp. VLSI Tech., Systems and Applications, pp. 113–117, 1997.
C. L. Wang and J. L. Lin, “Systolic Array Implementation of Multipliers for Finite Field GF(2m),” IEEE Trans. Circuits and Syst., vol. 38, no. 7, pp. 796–800, July 1991.
T. Blum and C. Paar, “High Radix Montgomery Modular Exponentiation on Reconfigurable Hardware”, IEEE Trans. Computers., vol. 50, no. 7, pp. 759–764, July 2001.
S.D. Han, C.H. Kim, and C.P. Hong, “Characteristic Analysis of Modular Multiplier for GF(2m),” Proc. of IEEK Summer Conference 2002, vol. 25, no. 1, pp. 277–280, 2002.
R. Tessier and W. Burleson, “Reconfigurable Computing for Digital Signal Processing: A Survey”, J. VLSI Signal Processing, vol. 28, no. 1, pp. 7–27, May 1998.
K. Compton and S. Hauck, “Reconfigurable Computing: A Survey of Systems and Software”, ACM Computing Surveys, vol. 34, no. 2, pp. 171–210, June 2002.
S. Y. Kung, VLSI Array Processors, Englewood Cliffs, NJ: Prentice Hall, 1988.
NIST, Recommended elliptic curves for federal government use, May 1999. http://csrc.nist.gov/encryption.
Altera, APEXTMII Programable Logic Device Family Data Sheet, Aug. 2000. http://www.altera.com/literature/lit-ap2.html.
C.H. Kim and C.P. Hong, “High Speed Division Architecture for GF(2m)”, Electronics Letters, vol. 38, no. 15, pp. 835–836, July 2002.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer
About this chapter
Cite this chapter
Kim, C.H., Hong, C.P., Kwon, S., Kwon, Y.K. (2005). A New Arithmetic Unit in GF(2M) for Reconfigurable Hardware Implementation. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_19
Download citation
DOI: https://doi.org/10.1007/1-4020-3128-9_19
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3127-4
Online ISBN: 978-1-4020-3128-1
eBook Packages: EngineeringEngineering (R0)