Abstract
This paper proposes modifications to standard island-style FPGAs that provide interconnect capable of scaling at the same rate as typical netlists, unlike traditionally tiled FPGAs. The proposal uses logical third and fourth dimensions to create increasing wire density for increasing logic capacity. The additional dimensions are mapped to standard two-dimensional silicon. This innovation will increase the longevity of a given cell architecture, and reduce the cost of hardware, CAD tool and Intellectual Property (IP) redesign. In addition, extra-dimensional FPGA architectures provide a conceptual unification of standard FPGAs and time-multiplexed FPGAs.
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References
M. J. Alexander, J. P. Cohoon, J. L. Colflesh, J. Karro, and G. Robins. Three-dimensional field-programmable gate arrays. In Proceedings of the IEEE International ASIC Conference, pages 253–256, September 1995.
M. J. Alexander, J. P. Cohoon, J. Karro J. L. Colflesh, E. L. Peters, and G. Robins. Placement and routing for three-dimensional FPGAs. In Fourth Canadian Workshop on Field-Programmable Devices, pages 11–18, Toronto, Canada, May 1996.
V. Betz and J. Rose. Effect of the prefabricated routing track distribution on FPGA area efficiency. IEEE Transactions on VLSI Systems, 6(3):445–456, September 1998.
C. E. Cheng. RISA: Accurate and efficient placement routability modeling. In Proceedings of IEEE/ACM International Conference on CAD (ICCAD), pages 690–695, November 1996.
A. DeHon. DPGA-coupled microprocessors: Commodity ICs for the early 21st century. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 31–39, Napa, CA, April 1994.
J. Depreitere, H. Neefs, H. Van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, and I. Veretennicoff. An optoelectronic 3-D field programmable gate array. In R. Hartenstein and M. Z. Servit, editors, Field-Programmable Logic: Architectures, Synthesis and Applications. 4th International Workshop on Field-Programmable Logic and Applications, pages 352–360, Prague, Czech Republic, September 1994. Springer-Verlag.
W. E. Donath. Placement and average interconnection lengths of computer logic. IEEE Transactions on Circuits and Systems, pages 272–277, April 1979.
Hongbing Fan, Jiping Liu, and Yu-Liang Wu. General models for optimum arbitrary-dimension fpga switch box designs. In Proceedings of IEEE/ACM International Conference on CAD (ICCAD), pages 93–98, November 2000.
A. El Gamal. Two-dimensional stochastic model for interconnections in master slice integrated circuits. IEEE Transactions on Circuits and Systems, 28(2):127–138, February 1981.
M. Hutton, J.P. Grossman, J. Rose, and D. Corneil. Characterization and parameterized random generation of digital circuits. In Proceedings of the 33rd ACM/SIGDA Design Automation Conference (DAC), pages 94–99, Las Vegas, NV, June 1996.
M. Hutton, J. Rose, and D. Corneil. Generation of synthetic sequential benchmark circuits. In 5th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, (FPGA 97), February 1997.
B. S. Landman and R. L. Russo. On pin versus block relationship for partions of logic circuits. IEEE Transactions on Computers, C-20:1469–1479, 1971.
M. Leeser, W. M. Meleis, M. M. Vai, W. Xu S. Chiricescu, and P. M. Zavracky. Rothko: A three-dimensional FPGA. IEEE Design and Test of Computers, 15(1):16–23, January 1998.
W. M. Meleis, M. Leeser, P. Zavracky, and M. M. Vai. Architectural design of a three dimensional FPGA. In Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI), pages 256–268, September 1997.
S. Scalera and J. R. Vazquez. The design and implementation of a context switching FPGA. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 78–85, Napa, CA, April 1998.
S. Trimberger. Scheduling designs into a time-multiplexed FPGA. In 6th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, (FPGA 98), pages 153–160, February 1998.
S. Trimberger, D. Carberry, A. Johnson, and J. Wong. A time-multiplexed FPGA. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 22–28, Napa, CA, April 1997.
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Schmit, H. (2005). Extra-dimensional Island-Style FPGAs. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_1
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DOI: https://doi.org/10.1007/1-4020-3128-9_1
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