Methodology for Development of High-κ Stacked Gate Dielectrics on III–V Semiconductors

Abstract

A comprehensive methodology for the development of gate dielectrics on III–V semiconductors is presented. This methodology has been motivated by the tremendous difficulties encountered during the development of gate dielectrics on GaAs. The understanding that modern gate dielectrics are typically layered structures with the immediate dielectric/semiconductor interface having substantially different (and often mutually exclusive) requirements compared to the bulk of the dielectric film in terms of materials, manufacturing, and suitable characterization techniques, is at the core of the proposed methodology. While capacitor-based characterization methods such as capacitance-voltage measurements which require to maintain quasi-equilibrium in the semiconductor remain an essential component, non-equilibrium techniques such as photoluminescence intensity have become a necessary ingredient. The application of the proposed methodology has led to high-κ stacked gate oxides on GaAs displaying a broad minimum of interface state density D _it ≤ 2 × 10¹¹ cm⁻² eV⁻¹ on n-type GaAs suggesting a U-shaped D _it distribution, an oxide relative dielectric constant of 20.8 ± 1, a breakdown field exceeding 4 MV/cm, and leakage currents of ≅ 2 × 10⁻⁸ A/cm² at an electric field of 1 MV/cm (SiO₂ equivalent field = 5.3 MV/cm). Potential extensions of the proposed methodology to high-κ gate dielectric development on elemental semiconductors such as Si and Ge and wide bandgap semiconductors such as GaN are further discussed.