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Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment pp 309–320Cite as

Theoretical Limit for the SiO2 Thickness in Silicon MOS Devices

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Part of the book series: NATO Science Series II: Mathematics, Physics and Chemistry ((NAII,volume 185))

Abstract

Fundamental limitations for the minimum thickness of the SiO2 layer as the gate insulator in silicon MOS devices, resulting from quantum-mechanical outflow of electron wave functions from the semiconductor region are considered.

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Author information

Authors and Affiliations

  1. Institute of Microelectronics and Optoelectronis, Warsaw University of Technology, Koszykowa 75, 00-662, Warsaw, Poland

    B. Majkusiak & J. Walczak

Authors
  1. B. Majkusiak
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  2. J. Walczak
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Editor information

Editors and Affiliations

  1. Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la-Neuve, Belgium

    Denis Flandre

  2. Institute of Semiconductor Physics, National Academy of Science of Ukraine, Kyiv, Ukraine

    Alexei N. Nazarov

  3. School of Electronics and Physical Sciences, University of Surrey, Guildford, UK

    Peter L.F. Hemment

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© 2005 Kluwer Academic Publishers

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Majkusiak, B., Walczak, J. (2005). Theoretical Limit for the SiO2 Thickness in Silicon MOS Devices. In: Flandre, D., Nazarov, A.N., Hemment, P.L. (eds) Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment. NATO Science Series II: Mathematics, Physics and Chemistry, vol 185. Springer, Dordrecht. https://doi.org/10.1007/1-4020-3013-4_36

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  • DOI: https://doi.org/10.1007/1-4020-3013-4_36

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-1-4020-3011-6

  • Online ISBN: 978-1-4020-3013-0

  • eBook Packages: EngineeringEngineering (R0)

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