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Further Possibilities of FG Device Compact Models

Reliability prediction and statistics

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Floating Gate Devices: Operation and Compact Modeling
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References

  1. Jan de Blauwe, Jan Van Houdt, Dirk Wellekens, Guido Groseneken, and Herman E. Maes, “SILC-related effects in flash-EEPROM’s-Part I: A quantitative model for steady-state SILC”, IEEE Trans. Electron Devices, vol. 45, no. 8, pp. 1751–1760, 1998.

    Google Scholar 

  2. Jan de Blauwe, Jan Van Houdt, Dirk Wellekens, Guido Groseneken, and Herman E. Maes, “SILC-related effects in flash-EEPROM’s-Part II: Prediction of steady-state SILC-related disturb characteristic,” IEEE Trans. Electron Devices, vol. 45, no. 8, pp. 1751–1760, 1998.

    Google Scholar 

  3. S. Satoh, G. Hemink, K. Hatakeyama, and S. Aritome, “Stress-Induced Leakage Current of tunnel oxide derived from Flash memory read-disturb characteristics,” IEEE Trans. Electron Dev., Vol. 45, N. 2, pp. 482–486, 1998.

    Google Scholar 

  4. L. Larcher, S. Bertulu, P. Pavan, “SILC effects on EEPROM memory cell reliability,” IEEE Trans. Device and Material Reliability, Vol. 2, N. 1, pp. 13–18, 2002.

    Google Scholar 

  5. H.P. Belgal, N. Righos, I. Kalastirsky, J.J. Peterson, R. Shiner, and N. Mielke, “A new reliability model for post-cycling charge retention of Flash memories,” in Proc. 40 th IEEE-IRPS, Dallas (USA), pp. 7–20, 2002.

    Google Scholar 

  6. R. Moazzami and C. Hu, “Stess-induced current in thin silicon dioxide films,” in Proc. IEDM, San Francisco (USA), pp. 139–142, 1992.

    Google Scholar 

  7. L. Larcher, A. Paccagnella, and G. Ghidini, “A new model of Stress Induced Leakage Current in gate oxides”, IEEE Trans. Electron Dev., Vol. 48, N. 2, pp. 285–288, 2001.

    Google Scholar 

  8. Kiyohiko Sakakibara, Natsuo Ajika, Katsumi Eikyu, Kiyoshi Ishikawa, and Hirokazu Miyoshi, “A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO2 films”, IEEE Trans. Electron Devices, vol. 44, no. 6, pp. 1002–1007, 1997

    Google Scholar 

  9. Shin-ichi Takagi, Naoki Yasuda, and Akira Toriumi, “A new I–V model for stress-induced leakage current including inelastic tunneling”, IEEE Trans. Electron Devices, vol. 46, no. 2, pp. 348–354, 1999.

    Google Scholar 

  10. B. Riccò, G. Gozzi, and M. Lanzoni, “Modeling and simulation of Stress-Induced Leakage Current in ultrathin SiO2 films,” IEEE Trans. Electron Devices, vol. 45, no. 7, pp. 1554–1560, 1998.

    Google Scholar 

  11. C. Lam, T. Sunaga, Y. Igarashi, M. Ichinose, K. Kitamura, C. Willets, J. Johnson, S. Mittl, F. White, H. Tang, T.-C. Chen, “Anomalous low temperature charge leakage mechanism in ULSI Flash memories,” in Proc. IEDM, San Francisco (USA), pp. 335–338, 2000.

    Google Scholar 

  12. H. Kameyama, Y. Okuyama, S. Kamohara, K. Kubota, H. Kume, K. Okuyama, Y. Manabe, A. Nozoe, H. Uchida, M. Hidaka, and K. Ogura, “A new data retention mechanism after endurance stress on Flash memory,” in Proc. 38 th IEEE-IRPS, San jose (USA), pp. 194–199, 2000.

    Google Scholar 

  13. D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, “Equivalent cell approach for extraction of the SILC distribution in Flash EEPROM cells,” IEEE Electron Devices Letters, Vol. 23, N. 1, pp. 40–42, 2002.

    Article  Google Scholar 

  14. P. J. Kuhn, A. Hoefler, T. Harp, B. Hornung, “A reliability methodology for low temperature data retention in floating gate non-volatile memories,” in Proc. 39 th IEEE-IRPS, Orlando (USA), pp. 266–270, 2001.

    Google Scholar 

  15. A. Modelli, F. Gilardoni, D. Ielmini, and A. S. Spinelli, “A new conduction mechanism for the anomalous cells in thin oxide Flash EEPROMs,” in Proc. 39 th IEEE-IRPS, Orlando (USA), pp. 61–66, 2001.

    Google Scholar 

  16. D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, “A new two-trap tunneling model for the anomalous SILC in Flash memories,” in Proc. INFOS, pp. 39–40, 2001.

    Google Scholar 

  17. F. Schuler, R. Degreave, P. Hendrickx, D. Wellekens, „Physical description of anoumaluos charge loss in floating gate based NVM’s and identification of its dominant parameter,” in Proc. 40 th IEEE-IRPS, Dallas (USA), pp. 26–33, 2002.

    Google Scholar 

  18. D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, “Statistical modeling or reliability and scaling projections for Flash memories,” in Proc. IEDM, Washington DC (USA), pp. 703–706, 2001.

    Google Scholar 

  19. R. Degraeve, F. Schuler, M. Lorenzini, D. Wellekens, P. Hendrickx, J. Van Houdt, L. Haspeslagh, G. Groseneken, G. Tempel, “Analitycal model for failure rate prediction due to anomalous charge loss of Flash memories,” in Proc. IEDM, Washington DC (USA), pp. 699–702, 2001.

    Google Scholar 

  20. A. Scarpa, P. Reis, G. Ghibaudo, A. Paccagnella, G. Pananakakis, J. Brini, G. Ghidini and C. Papadas, “Stress Induced Leakage Current Dependence on Oxide Thickness, Technology and stress level,” in Proc. of the 27th European Solid-State Device Research Conference (ESSDERC 97), pp. 592–595, Stuttgart (Germany), 22–24 September 1997.

    Google Scholar 

  21. A. Scarpa, Ph.D. Thesis, Chap.7, University of Padova, Italy, 1998.

    Google Scholar 

  22. K. Sakakibara, N. Ajika, M. Hatanaka, and H. Miyoshi, “A quantitative analysis of stress induced excess current in SiO2 films”, in IRPS Tech. Dig., p. 100, 1996

    Google Scholar 

  23. A. Schenk and H. Hermann, “A new model for long term charge loss in EPROMs,” Ext. Abstract of the International Conference on Solid State Devices and Materials (SSDM), pp. 494–496, Yokohama (Japan), 1994.

    Google Scholar 

  24. M. Hermann and A. Schenk, „Field and high temperature dependence on the long term charge loss in erasable programmable read only memories: Measurements and Modeling,” J. Appl. Phys., Vol. 77, N. 9, pp. 4522–4540, 1995.

    Article  Google Scholar 

  25. Shin-ichi Takagi, Naoki Yasuda and Akira Toriumi, “Experimental evidence of inelastic tunneling and new I–V model for stress-induced leakage current”, in IEDM Tech. Dig., pp. 323–326, 1996.

    Google Scholar 

  26. J. Wu, L.F. Register, and E. Rosenbaum, “Trap-assisted tunneling current through ultra-thin oxide”, in IRPS Tech. Dig., pp. 396–399, 1999.

    Google Scholar 

  27. Paul E. Nicollian, Mark Rodder, Douglas T. Grider, Peijun Chen, Robert M. Wallace, and Sunil V. Hattangady, “Low voltage stress-induced leakage current in ultrathin gate oxides”, in IRPS Tech. Dig., pp. 400–404, 1999.

    Google Scholar 

  28. C.T. Liu, A. Ghetti, Y. Ma, G. Alers, C.P. Chang, K.P. Cheung, J.I. Colonell, W.Y.C. Lai, C.S. Pai, R. Liu, H. Vaidya, and J.T. Clemens, “Intrinsic and stress-induced traps in the direct tunneling current of 2.3–3.8 nm oxides and unified characterization methodologies of sub-3nm oxides”, in IEDM Tech. Dig., pp. 85–88, 1997.

    Google Scholar 

  29. D. Ielmini, A. S. Spinelli, M. A. Rigamonti, A. L. Lacaita, “Modeling of SILC based on electron and hole tunneling. II. Steady-state,” IEEE Trans. Electron Dev., Vol. 47, N. 6, pp. 1266–1272, 2000.

    Google Scholar 

  30. Anthony I. Chou, Kafai Lai, Kiran Kumar, Prasenjit Chowdhury, and Jack C. Lee, “Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism”, Appl. Phys. Lett., vol. 70, no. 25, pp. 3407–3409, 1997.

    Article  Google Scholar 

  31. N. Yasuda, N. Patel, and A. Toriumi, “A two-step tunnelling model for stress induced leakage currents in ultra-thin silicon dioside films,” Ext. Abst. Solid State Devices and Materials, pp. 847–850, 1993.

    Google Scholar 

  32. L. Larcher, “Statistical Simulation of Leakage Currents in MOS and Flash Memory Devices with a new multi-Phonon Trap-Assisted Tunneling Model,” to be published on Trans. On Electron Devices.

    Google Scholar 

  33. G. Cellere, L. Larcher, M.G. Valentini, and A. Paccagnella, “Micro breakdown in small-area ultra-thin gate oxide,” on Trans. on Electron Devices, Vol. 49, N.8, pp. 1367–1374, 2002.

    Google Scholar 

  34. P. Cappelletti, R. Bez, D. Cantarelli, and L. Frattin, “Failure mechanism of Flash cell in program/erase cycling,” in IEDM Tech. Dig., 1994, pp. 291–294.

    Google Scholar 

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(2004). Further Possibilities of FG Device Compact Models. In: Floating Gate Devices: Operation and Compact Modeling. Springer, Boston, MA. https://doi.org/10.1007/1-4020-2613-7_5

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  • DOI: https://doi.org/10.1007/1-4020-2613-7_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7731-9

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