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Principles of Floating Gate Devices

Basic process, operation, physical aspects and reliability

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Floating Gate Devices: Operation and Compact Modeling

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References

  1. L. Van den Hoven, A. M. Goethals, K. Ronse, M. Van Bavel, and G. Vandenberghe, “Lithography for sub 90 nm applications,” in IEDM Tech. Dig., pp.3–8, 2002.

    Google Scholar 

  2. D. Canali, D. Fattori, G. Ginami, G. Girardi, P. Scintu, L. Tarchini, D. Tricarico, “Survey on Flash technology with specific attention to the critical Process Parameters related to the design,” in Proc. of the IEEE, Vol. 41(4), pp.503–522, 2003.

    Google Scholar 

  3. R. A. Bianchi, G. Bounche, and O. Roux-dit-Buison, “Accurate Modeling of Trench Isolation Induced Stress effects on MOS Electrical Performance,” in IEDM Tech. Dig., pp.117–120, 2002.

    Google Scholar 

  4. J.D. Bude, M.R. Pinto, and R.K. Smith, “Monte Carlo simulation of the CHISEL-Flash memory cell,” IEEE Trans. Electron Dev., Vol. ED-47(10), pp.1873–1881, 2000.

    Google Scholar 

  5. J.D. Bude, M. Mastrapasqua, M.R. Pinto, R.W. Gregor, P.J. Kelley, R.A. Kohler, C.W. Leung, Y. Ma, R.J. McPartland, P.K. Roy, R. Singh, “Secondary Electron Flash–a high performance, low power Flash technology for 0.35 m and below,” in IEDM Tech. Dig., pp.279–282, 1997.

    Google Scholar 

  6. J. D. Bude, A. Frommer, M. R. Pinto, and G. R. Weber, “EEPROM/flash sub 3.0V drain-source bias hot carrier writing,” in IEDM Tech. Dig., pp.989–991, 1995.

    Google Scholar 

  7. Y. Leblebici, and S.-M. Kang, “Modeling of nMOS transistors for simulating of hot-carrier-induced device and circuit degradation”, IEEE Trans. on CAD., Vol. 11(2), pp.235–246, 1992.

    Google Scholar 

  8. P. Chen, L. Wu, G. Zhang, and Z. Liu, “A unified compact scalable ΔID model for hot carrier reliability simulation,” in Proc. IEEE 37th Annual International Reliability Physics Symposium, San Diego, California, 1999, pp. 243–248.

    Google Scholar 

  9. C.-M. Yih, S.-M. Cheng, and S.S. Chung, “A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage,” IEEE Trans. Electron Dev., Vol. ED-45(11), pp.2343–2348, 1998.

    Google Scholar 

  10. C. Chen, Z.-Z. Liu, and T.-P. Ma, “Analysis of enhanced hot-carrier effects in scaled Flash memory devices,” IEEE Trans. Electron Dev., Vol. ED-45(7), pp.1524–1530, 1998.

    Google Scholar 

  11. S.S. Chung, C.-M. Yih, S.-M. Cheng, and M.-S. Liang, “A new technique for hot carrier reliability evaluations of Flash memory cell after long-term program/erase cycle,” IEEE Trans. Electron Dev., Vol. ED-46(9), pp.1833–1889, 1999.

    Google Scholar 

  12. S. Keeney, R. Bez, D. Cantarelli, F. Piccinini, A. Mathewson, L. Ravazzi, C. Lombardi, “Complete Transient Simulation of Flash EEPROM Devices”, IEEE Trans. Electron Dev., Vol. ED-39(12), pp.2750–2757, 1992.

    Google Scholar 

  13. C. Fiegna, F. Venturi, M. Melanotte, E. Sangiorgi, and Bruno Riccò, “Simple and efficient modeling of EPROM writing,” IEEE Trans. Electron Dev., Vol. ED-38(3), pp.603–610, 1991.

    Google Scholar 

  14. C. Hu, “Lucky-electron model of channel hot electron emission,” in IEDM Tech. Dig., pp.223–226, 1979.

    Google Scholar 

  15. B. Eitan, and D. Frohman-Bentchkowsky, “Hot-Electron injection into the oxide in n-channel MOS devices,” IEEE Trans. Electron Dev., Vol. ED-28(3), pp.328–340, 1981.

    Google Scholar 

  16. P. E. Cottrell, R. R. Trooutman, and T. H. Ning, “Hot-electron emission in n-channel IGFET’s,” IEEE Trans. Electron Devices, vol. 26, no. 4, pp. 520–532, 1979.

    Google Scholar 

  17. G. A. Baraff, “Distribution functions and ionization rates for hot-electrons in semiconductors,” Phys. Rev., vol. 128, no. 6, pp. 2507–1517, 1962.

    Article  MATH  Google Scholar 

  18. S. Tam, P. K. Ko, C. Hu, and R. Muller, “Correlation between substrate and gate currents in MOSFET’s,” IEEE Trans. Electron Devices, vol. 29, no. 11, pp. 1744–1744, 1982.

    Google Scholar 

  19. E. Takeda, H. Kune, T. Toyabe, and S. Asai, “Submicrometer MOSFET structure for minimizing hot-carrier generation,” IEEE Trans. Electron Devices, vol. 29, no. 4, pp. 611–618, 1982.

    Google Scholar 

  20. K. Hess and C. T. Sah, ”Hot carriers in Silicon surface inversion layers,” J. Appl. Phys., vol. 45, p. 1254, 1974.

    Article  Google Scholar 

  21. K. R. Hofmann, C. Werner, W. Weber, and G. Dorda,“Hot-electrons and hole-emission effects in short n-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 32, no. 3, pp. 691–699, 1985.

    Google Scholar 

  22. B. Riccò, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, and A. Modelli, “Nonvolatile multilevel memories for digital applications,“ Proc. of the IEEE, Vol. 86, N. 12, pp.2399–2421, 1998.

    Google Scholar 

  23. L. Esaki, ”Long journey into tunneling,” in Proc. IEEE, vol. 62, pp. 825–831, 1974.

    Google Scholar 

  24. J. Moll, Physics of Semiconductors. New York: McGraw-Hill, 1964.

    Google Scholar 

  25. M. Lenziger and E.H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278–283, 1969.

    Google Scholar 

  26. P. Olivo, T. Nguyen, and B. Riccò, “High-field-induced degradation in ultra thin SiO2 films,” IEEE Trans. Electron Dev., Vol. ED-35(12), pp. 2259–2267, 1988.

    Google Scholar 

  27. J. Tang and K. Hess, “Theory of hot electron emission from silicon into silicon dioxide,” J. Appl. Phys., vol. 54, pp. 5145–5151, 1983.

    Google Scholar 

  28. J. Suňè, P. Olivo, and B. Riccó, “Quantum-mechanical modeling of accumulation layers in MOS structure,” IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1732–1738, 1992.

    Google Scholar 

  29. P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, “Failure mechanisms of Flash cell in program/erase cycling,” IEDM Tech. Dig., pp. 291–294, 1994.

    Google Scholar 

  30. K. T. San, C. Kaya, D. K. Y. Liu, T. P. Ma, and P. Shah, “A new technique for determining the capacitive coupling coefficients in FLASH EPROM’s,” IEEE Electron Device Lett., vol. 13, no. 6, pp. 328–331, 1992.

    Article  Google Scholar 

  31. S. Aritome, R. Shirota, G. Hemnik, T. Endoh, and F. Masuoka, “Reliability issues of Flash memory cells,” in Proc. IEEE, vol. 81, pp. 776–788, May 1993.

    Article  Google Scholar 

  32. C. Papadas, G. Ghibaudo, G. Pananakakis, C. Riva, P. Ghezzi, C. Gounelle, and P. Mortini, “Retention characteristics of single-poly EEPROM cells,” in Proc. European Symp. Reliability of Electronic Devices, Failure Physics and Analysis (ESREF), Bordeaux, France, Oct. 7–10, 1991, pp. 517–522.

    Google Scholar 

  33. A. Watts, “Built-in reliability for 10 FITS performance on EPROM and Flash memory,” SGS-Thomson Microelectronic, Agrate Brianza, Italy, Tech. Art. TA 109, Nov. 1991.

    Google Scholar 

  34. P. L. Hefley and J. W. McPherson, in Proc. IRPS, 1988, p. 176.

    Google Scholar 

  35. G. Crisenza, R. Annunziata, E. Camerlenghi, and P. Cappelletti, “Non volatile memories: Issues, challenges and trends for the 2000’s scenario,” in Proc. ESSDERC’96, G. Baccarani and M. Rudan, Eds. Bologna, Italy: Editions Frontieres, 1996, pp. 121–130.

    Google Scholar 

  36. S. Mori, Y. Yamaguchi, M. Sato, H. Meguro, H. Tsunoda, E. Kamiya, K. Yoshikawa, N. Arai, and E. Sakagami, “Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices,” IEEE Trans. Electron Devices, vol. 43, no. 1, pp. 47–53, 1996.

    Article  Google Scholar 

  37. S. Maramatsu, T. Kubota, N. Nishio, H. Shirai, M. Matsuo, N. Kodama, M. Horikawa, S. Saito, K. Arai, and T. Okazawa, “The solution of over-erase problem controlling poly-Si grain size modified principles for Flash memories,” IEDM Tech. Dig., 1994, pp. 847–850.

    Google Scholar 

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(2004). Principles of Floating Gate Devices. In: Floating Gate Devices: Operation and Compact Modeling. Springer, Boston, MA. https://doi.org/10.1007/1-4020-2613-7_2

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  • DOI: https://doi.org/10.1007/1-4020-2613-7_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7731-9

  • Online ISBN: 978-1-4020-2613-3

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