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References
Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI, New York, NY: Addison-Wesley, 1990.
Batterywala, S., Shenoy, N., Nicholls, W., and Zhou, H., Track assignment: a desirable intermediate step between global routing and detailed routing, Proceedings of the International Conference on Computer-Aided Design, pp. 59–66, 2002.
Bernard, J., The IC yield problem: A tentative analysis for MOS/SOS circuits, IEEE Transactions on Electron Devices 25(8), pp. 939–944, Aug. 1978.
Borkar, S., Obeying Moore’s law beyond 0.18 micron, Proceedings of the International Conference on ASIC/SOC, pp. 26–31, 2000.
Dennard, R. H., Gaensslen, F. H., Yu, H.-N., Rideout, V. L., Bassous, E., and LeBlanc, A. R., Design of ion-implanted MOSFETs with very small physical dimensions, IEEE Journal of Solid-State Circuits 9(5), pp. 256–268, Oct. 1974.
Ferris-Prabhu, A. V., Modeling of Critical Area in Yield Forecasts, IEEE Journal of Solid-State Circuits SC-20(4), pp. 878–880, Aug. 1985.
International Technology Roadmap for Semiconductors, 2005 ed., available at http://www.itrs.net/Links/2005ITRS/Interconnect2005.pdf.
Maly, W., and Deszczka, J., Yield Estimation Model for VLSI Artwork Evaluation, Electronics Letters 19(6), pp. 226–227, March 1983.
Moore, G. E., Cramming more components onto integrated circuits, Electronics Magazine, pp. 114–117, April 1965.
Moore, G. E., Progress in digital integrated electronics, Proceedings of the International Electron Devices Meeting, vol. 21, pp. 11–13, 1975.
Moore, G. E., No exponential is forever: but “forever” can be delayed!, Proceedings of the International Solid-State Circuits Conference, vol. 1, pp. 20–23, 2003.
Saxena, P., Menezes, N., Cocchini, P., and Kirkpatrick, D. A., Repeater scaling and its impact on CAD, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(4), pp. 451–463, April 2004.
Sylvester, D., and Keutzer, K., Getting to the bottom of deep submicron II: A global wiring paradigm, Proceedings of the International Symposium on Physical Design, pp. 193–200, 1999.
TSMC unveils NexsysSM 90-nanometer process technology, 2004, available at http://www.tsmc.com/english/b_technology/b01_platform/b010101_90nm.htm.
Warner, R. M., Applying a composite model to the IC yield problem, IEEE Journal of Solid-State Circuits 9(3), pp. 86–95, June 1974.
X Initiative, First 90 nm functional silicon using X architecture, 2003, available at http://www.xinitiative.org/img/Toshiba_100803_Yoshimori.pdf.
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(2007). An Introduction to Routing Congestion. In: Routing Congestion in VLSI Circuits: Estimation and Optimization. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-48550-3_1
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DOI: https://doi.org/10.1007/0-387-48550-3_1
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