Skip to main content
SpringerLink
Log in

Hybrid Techniques

  • Chapter
Software-Implemented Hardware Fault Tolerance

  • 778 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. Mahmood, E. J. McCluskey, “Concurrent error detection using watchdog processors-a survey”, IEEE Transaction on Computers, Vol. 37, No. 2, February 1988, pp. 160–174.

    Article  Google Scholar 

  2. F. Rodriguez, J.C. Campelo, J.J. Serrano, “Improving the interleaved signature instruction stream technique”, IEEE Canadian Conference on Electrical and Computer Engineering, 2003, Vol. 1, pp. 93–96

    Google Scholar 

  3. F. Rodriguez, J.C. Campelo, J.J. Serrano, “A Watchdog Processor Architecture with Minimal Performance Overhead”, International Conference on Computer Safety, Reliability and Security, 2002, pp. 261–272

    Google Scholar 

  4. J. Ohlsson, M. Rimen, “Implicit Signature Checking”, Proc. 25th International Symposium on Fault-Tolerant Computing, 1995, pp. 218–227.

    Google Scholar 

  5. J. Ohlsson, M. Rimen, U. Gunneflo, “A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog”, Twenty-Second International Symposium on Fault-Tolerant Computing, 1992, FTCS-22, pp. 316–325.

    Google Scholar 

  6. N.R. Saxena, E.J. McCluskey, “Control Flow Checking Using Watchdog Assists and Extended-Precision Checksums”, IEEE Transactions on Computers, Vol. 39, No. 4, Apr. 1990, pp. 554–559.

    Article  Google Scholar 

  7. N.R. Saxena, E.J. McCluskey, “Control-flow checking using watchdog assists and extended-precision checksums”, Digest of Papers, of Nineteenth International Symposium on Fault-Tolerant Computing, 21–23 June 1989, pp. 428–435.

    Google Scholar 

  8. N.J. Warter, W.-m.W. Hwu, “A software based approach to achieving optimal performance for signature control flow checking”, FTCS-20. Digest of Papers of 20th International Symposium on Fault-Tolerant Computing, 26–28 June 1990 pp. 442–449.

    Google Scholar 

  9. K. Wilken, J.P. Shen, “Continuous signature monitoring: efficient concurrent-detection of processor control errors”, Proc. IEEE International Test Conference, 1988, pp. 914–925.

    Google Scholar 

  10. K. Wilken, J.P. Shen, “Continuous Signature Monitoring: Low-Cost Concurrent Detection of Processor Control Errors”, IEEE Trans. on Computer-Aided Design, Vol. 9, No. 6, June 1990, pp. 629–641.

    Article  Google Scholar 

  11. K.D. Wilken, “Optimal signature placement for processor-error detection using signature monitoring”, Digest of Papers of Twenty-First International Symposium on Fault-Tolerant Computing, 1991, pp. 326–333.

    Google Scholar 

  12. K.D. Wilken, “An optimal graph-construction approach to placing program signatures for signature monitoring”, IEEE Transactions on Computers, Vol. 42, Issue: 11, Nov. 1993, pp. 1372–1381.

    Article  Google Scholar 

  13. J.P. Shen and M.A. Schuette, “On-line Self-Monitoring Using Signatured Instruction Streams”, Proc. IEEE International Test Conference, 1983, 1983, pp. 275–282.

    Google Scholar 

  14. M. Namjoo, “Techniques for concurrent testing of VLSI processor operation”, in IEEE International Test Conference, 1982, Nov. 15–18, 1982, pp. 461–468.

    Google Scholar 

  15. M. Namjoo, “CERBERUS-16: An architecture for a general purpose watchdog processor”, Digest of Papers of Thirteenth International Symposium on Fault-Tolerant Computing, 1983, pp. 216–219.

    Google Scholar 

  16. M. Namjoo, E.J. McCluskey, “Watchdog processors and capability checking”, Digest of Papers of Twelfth International Symposium on Fault-Tolerant Computing, FTCS-12, 1982, pp. 245–248

    Google Scholar 

  17. A. Mahmood, D.J. Lu, and E.J. McCluskey, “Concurrent fault detection using a watchdog processor and assertions”, Proc. IEEE International Test Conference, 1983, pp. 622–628

    Google Scholar 

  18. S.H. Saib, “Distributed architectures for reliability”, Proc. AIAA Computer in Aerospace Conference, 1979, pp. 458–462

    Google Scholar 

  19. A. Mahmood, A. Ersoz, E.J. McCluskey, “Concurrent system level error detection using a watchdog processor”, Proc. IEEE International Test Conference, 1985, pp. 145–152

    Google Scholar 

  20. T. Sridhar and S.M. Thatte, “Concurrent checking of program flow in VLSI processors”, in IEEE International Test Conference, 1982, Nov. 15–18, 1982, pp. 191–199.

    Google Scholar 

  21. A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, “A watchdog processor to detect data and control flow errors”, On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE, 7–9 July 2003, pp. 144–148

    Google Scholar 

  22. J.B. Eifert, J.P. Shen, “Processor Monitoring Using Asynchronous Signatured Instruction Streams”, in Dig., 14th Int. Conf. Fault-Tolerant Comput., FTCS-14, Kissimmee, FL, June 20–22, 1984, pp. 394–399

    Google Scholar 

  23. S.J. Upadhyaya, B. Ramamurthy, “Concurrent process monitoring with no reference signatures”, IEEE Transactions on Computers, Vol.: 43, Issue: 4, April 1994, pp. 475–480

    Article  Google Scholar 

  24. T. Michel, R. Leveugle and G. Saucier, “A New Approach to Control Flow Checking without Program Modification”, Proc. FTCS-21, 1991, pp. 334–341.

    Google Scholar 

  25. H. Madeira, J. Camoes, J.G. Silva, “A watchdog processor for concurrent error detection in multiple processor system”, Microprocessors and Microsystems, Vol. 15, No. 3, April 1991, pp. 123–131

    Article  Google Scholar 

  26. X. Delord, G. Saucier, “Control flow checking in pipelined RISC microprocessors: the Motorola MC88100 case study”, Proceedings of Euromicro’ 90 Workshop on Real Time, 6–8 June 1990, pp. 162–169.

    Google Scholar 

  27. M.Z. Khan, J.G. Tront, “Detection of transient faults in microprocessors by concurrent monitoring”, Test Conference, 1989. Proceedings. ‘Meeting the Tests of Time’., International, 29–31 Aug. 1989, p. 948

    Google Scholar 

  28. S.P. Tomas and J.P. Shen, “A roving monitoring processor for detection of control flow errors in multiple processor systems”, in Proc. IEEE Int. Conf. Comput. Design: VLSI Comput., Port Chester, NY, Oct. 7–10, 1985, pp. 531–539.

    Google Scholar 

  29. M. Namjoo, “CERBERUS-16: An Architecture for a General Purpose Watchdog Processor”, Proc. Symposium on Fault-Tolerant Computing, 1983, pp. 216–219.

    Google Scholar 

  30. D.J. Lu, “Watchdog processor and structural integrity checking”, IEEE Trans. Computers, vol. C-31, 1982 Jul, pp. 681–685.

    Google Scholar 

  31. J.R. Kane and S.S. Yau, “Concurrent software fault detection”, IEEE Trans. Software Eng., vol. SE-1, pp. 87–99, Mar. 1975.

    MathSciNet  Google Scholar 

  32. G. Miremadi, J. Ohlsson, M. Rimen, J. Karlsson, “Use of Time and Address Signatures for Control Flow Checking”, International Conference on Dependable Computing for Critical Applications (DCCA-5), 1995, pp. 113–124.

    Google Scholar 

  33. H. Madeira and J.G. Silva, “On-line Signature Learning and Checking”, Dependable Comp. For Critical Applications, DCCA-2, Springer-Verlag, 1992.

    Google Scholar 

  34. B. Ramamurthy, S. Upadhyaya, “Watchdog processor-assisted fast recovery in distributed systems”, International Conference on Dependable Computing for Critical Applications (DCCA-5), 1995, pp. 125–134

    Google Scholar 

  35. A. Mahmood and E.J. McCluskey, “Watchdog Processor: Error Coverage and Overhead”, 15th Ann. Int’l Symp. Fault-Tolerant Computing (FTCS-15), pp. 214–219, June 1985.

    Google Scholar 

  36. V.S. Iyengar and L.L. Kinney, “Concurrent fault detection in microprogrammed control units”, IEEE Trans. Comput., vol. C-34, pp. 810–821, Sept. 1985.

    Google Scholar 

  37. D. J. Lu, “Watchdog processor and VLSI”, in Proc. Nat. Electron. Conf., vol. 34, Chicago, IL, Oct. 27–28, 1980, pp. 240–245.

    Google Scholar 

  38. S.S. Yau, F.-C. Chen, “An Approach to Concurrent Control Flow Checking”, IEEE Transactions on Software Engineering, Vol. SE-6, No. 2, March 1980, pp. 126–137.

    MathSciNet  Google Scholar 

  39. S.M. Ornstein, W.R. Crowther, M.F. Kraley, R.D. Bressler, A. Michel, and F.E. Heart, “Pluribus — A reliable multiprocessor”, in Proc. AFIPS Conf., vol. 44, Anahein, CA, May 19–22, 1975, pp. 551–559.

    Google Scholar 

  40. J. R. Connet, E. J. Pasternak, and B.D. Wagner, “Software defenses in real time control systems”, in Dig. Int. Symp. Fault Tolerant Comput., FTCS-2, Newton, MA, June 19–21, 1972, pp. 94–99.

    Google Scholar 

  41. J. S. Novak and L.S. Tuomenoksa, “Memory mutilation in stored program controlled telephone systems”, in Conf. Rec. 1970 Int. Conf. Commun., vol. 2, 1970, pp. 43–32 to 43–45.

    Google Scholar 

  42. S.F. Daniels, “A concurrent test technique for standard microprocessors”, in Dig. Papers Compcon Spring 83, San Francisco, CA, Feb. 28–Mar. 3, 1983, pp. 389–394.

    Google Scholar 

  43. P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante, “An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits”, Journal of Electronic Testing: Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261–271

    Article  Google Scholar 

  44. http://www.eembc.org

    Google Scholar 

  45. N. Oh, S. Mitra, E.J. McCluskey, “ED4I: error detection by diverse data and duplicated instructions”, IEEE Transactions on Computers, Vol. 51, No. 2, Feb. 2002, pp. 180–199

    Article  Google Scholar 

  46. K. H. Huang, J. A. Abraham, “Algorithm-Based Fault Tolerance for Matrix Operations”, IEEE Transaction on Computers, vol. 33, Dec 1984, pp. 518–528

    MATH  Google Scholar 

  47. P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante, “Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors”, IEEE Transaction on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231–2236

    Article  Google Scholar 

  48. O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante, “Soft-error Detection Using Control Flow Assertions”, IEEE Int.l Symp. on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581–588

    Google Scholar 

  49. L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante, “Hybrid Soft Error Detection by means of Infrastructure IP cores”, IEEE International On-Line Testing Symposium, 2004, pp. 79–84

    Google Scholar 

  50. P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante, “Hybrid Soft Error Detection by means of Infrastructure IP cores”, IEEE International Conference on Dependable Systems and Networks, 2005, pp. 50–58

    Google Scholar 

  51. P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante, “A new Hybrid Fault Detection Technique for Systems-on-a-Chip”, accepted for publication on IEEE Transactions on Computer, 2006

    Google Scholar 

  52. A. Rajabzadeh, M. Mohandespour, G. Miremadi, “Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features”, Proc. of the 10-th IEEE Pacific Rim International Symposium on Dependable Computing, 2004, pp. 49–54

    Google Scholar 

  53. A. Rajabzadeh, “Experimental Evaluation of Master/Checker Architecture Using Power Supply-and Software-Based Fault Injection”, Proc. of the 10-th IEEE On-Line Testing Symposium, 2004, pp. 239–244

    Google Scholar 

  54. A. Rajabzadeh, “A 32-bit COTS-based Fault-Tolerant Embedded System”, Proc. Of the 11-th IEEE On-Line Testing Symposium, 2005

    Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer Science+Business Media, LLC

About this chapter

Cite this chapter

(2006). Hybrid Techniques. In: Software-Implemented Hardware Fault Tolerance. Springer, Boston, MA . https://doi.org/10.1007/0-387-32937-4_5

Download citation

  • DOI: https://doi.org/10.1007/0-387-32937-4_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-26060-0

  • Online ISBN: 978-0-387-32937-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation