Abstract
Chips containing reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based systems. Using embedded cores enables the design of high-complexity systems-on-chip with densities as high as millions of gates on a single die. The increase in the use of pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately, test solutions need to be incorporated into individual cores and then the tests from individual cores need to be scheduled and assembled into a chip level test strategy. However with the increased usage of cores from multiple and diverse sources, it is essential to create standard mechanisms to make core test plug-and-play possible. This chapter presents in general the challenges of testing core-based system-chips and describes their corresponding test solutions. It concentrates on the common test requirements and strategies
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© 2006 Springer
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Zorian, Y. (2006). Embedded Core-based System-on-Chip Test Strategies. In: Reis, R., Lubaszewski, M., Jess, J.A. (eds) Design of Systems on a Chip: Design and Test. Springer, Boston, MA. https://doi.org/10.1007/0-387-32500-X_11
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DOI: https://doi.org/10.1007/0-387-32500-X_11
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