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Multiscale Optimization in VLSI Physical Design Automation

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Multiscale Optimization Methods and Applications

Part of the book series: Nonconvex Optimization and Its Applications ((NOIA,volume 82))

Summary

The enormous size and complexity of current and future integrated circuits (IC’s) presents a host of challenging global, combinatorial optimization problems. As IC’s enter the nanometer scale, there is increased demand for scalable and adaptable algorithms for VLSI physical design: the transformation of a logical-temporal circuit specification into a spatially explicit one. There are several key problems in physical design. We review recent advances in multiscale algorithms for three of them: partitioning, placement, and routing.

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References

  1. C. Alpert, J.-H. Huang, and A.B. Kahng. Multilevel circuit partitioning. In Proc. 34th IEEE/ACM Design Automation Conf., 1997.

    Google Scholar 

  2. C. Alpert and A. Kahng. A hybrid multilevel/genetic approach for circuit partitioning. In In Proceedings of the Fifth ACM/SIGDA Physical Design Workshop, pages 100–105, 1996.

    Google Scholar 

  3. S.B. Akers. A modification of Lee’s path connection algorithm. IEEE Trans. on Computers, EC-16:97–98, Feb. 1967.

    Google Scholar 

  4. Christoph Albrecht. Provably good global routing by a new approximation algorithm for multicommodity flow. In Proc. International Symposium on Physical Design, pages 19–25, Mar. 2000.

    Google Scholar 

  5. C.J. Alpert. The ISPD98 circuit benchmark suite. In Proc. Intl Symposium on Physical Design, pages 80–85, 1998.

    Google Scholar 

  6. W.L. Briggs, V.E. Henson, and S.F. McCormick. A Multigrid Tutorial. SIAM, Philadelphia, second edition, 2000.

    Google Scholar 

  7. M. Burstein and R. Pelavin. Hierarchical channel router. Proc. of 20th Design Automation Conference, pages 519–597, 1983.

    Google Scholar 

  8. V. Betz and J. Rose. VPR: A new packing, placement, and routing tool for FPGA research. In Proc. Intl. Workshop on FPL, pages 213–222, 1997.

    Google Scholar 

  9. A. Brandt and D. Ron. Multigrid Solvers and Multilevel Optimization Strategies, chapter 1 of Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, 2002.

    Google Scholar 

  10. U. Brenner and A. Rohe. An effective congestion-driven placement framework. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22(4):387–394, April 2003.

    Article  Google Scholar 

  11. A. Brandt. Multi-level adaptive solutions to boundary value problems. Mathematics of Computation, 31(138):333–390, 1977.

    Article  MATH  MathSciNet  Google Scholar 

  12. A. Brandt. Algebraic multigrid theory: The symmetric case. Appl. Math. Comp., 19:23–56, 1986.

    Article  MATH  MathSciNet  Google Scholar 

  13. A. Brandt. Multiscale scientific computation: Review 2001. In T. Barth, R. Haimes, and T. Chan, editors, Multiscale and Multiresolution Methods. Springer Verlag, 2001.

    Google Scholar 

  14. M.A. Breuer. Min-cut placement. J. Design Automation and Fault Tolerant Comp., 1(4):343–362, Oct 1977.

    Google Scholar 

  15. Cadence Design Systems Inc. Envisia ultra placer reference. In http://www.cadence.com, QPlace version 5.1.55, compiled on 10/25/1999.

    Google Scholar 

  16. A.E. Caldwell, A.B. Kahng, and I.L. Markov. Improved algorithms for hypergraph partitioning. In Proc. IEEE/ACM Asia South Pacific Design Automation Conf., 2000.

    Google Scholar 

  17. C. Chang and J. Cong. Pseudo pin assignment with crosstalk noise control. In Proc. International Symposium on Physical Design, Apr 2000.

    Google Scholar 

  18. T.F. Chan, J. Cong, T. Kong, J. Shinnerl, and K. Sze. An enhanced multilevel algorithm for circuit placement. In Proc. IEEE International Conference on Computer Aided Design, San Jose, CA, Nov 2003.

    Google Scholar 

  19. T.F. Chan, J. Cong, T. Kong, and J. Shinnerl. Multilevel optimization for large-scale circuit placement. In Proc. IEEE International Conference on Computer Aided Design, pages 171–176, San Jose, CA, Nov 2000.

    Google Scholar 

  20. T.F. Chan, J. Cong, T. Kong, and J. Shinnerl. Multilevel Circuit Placement, chapter 4 of Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, Boston, 2003.

    Google Scholar 

  21. C.C. Chang, J. Cong, Z. Pan, and X. Yuan. Physical hierarchy generation with routing congestion control. In Proc. ACM International Symposium on Physical Design, pages 36–41, San Diego, CA, Apr 2002.

    Google Scholar 

  22. C. Chang, J. Cong, M. Romesis, and M. Xie. Optimality and scalability study of existing placement algorithms. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pages 537–549, 2004.

    Google Scholar 

  23. T.F. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proc. Int’l Symp. on Phys. Design, pages 185–192, 2005.

    Google Scholar 

  24. C-C. Chang, J. Cong, and M. Xie. Optimality and scalability study of existing placement algorithms. In Proc. Asia South Pacific Design Automation Conference, pages 621–627, 2003.

    Google Scholar 

  25. C.C. Chang, J. Cong, and M. Xie. Optimality and scalability study of existing placement algorithms. In Asia South Pacific Design Automation Conference, pages 325–330, Kitakyushu, Japan, Jan 2003.

    Google Scholar 

  26. J. Cong, J. Fang, and K.Y. Khoo. An implicit connection graph maze routing algorithm for ECO routing. In Proc. International Conference on Computer Aided Design, pages 163–167, Nov. 1999.

    Google Scholar 

  27. J. Cong, J. Fang, and K.Y. Khoo. DUNE: A multi-layer gridless routing system with wire planning. In Proc. International Symposium on Physical Design, pages 12–18, Apr. 2000.

    Google Scholar 

  28. J. Cong, J. Fang, and Y. Zhang. Multilevel approach to full-chip gridless routing. Proc. IEEE International Conference on Computer Aided Design, pages 396–403, 2001.

    Google Scholar 

  29. J. Cong, Lei He, C.-K. Koh, and P. Madden. Performance optimization of VLSI interconnect layout. Intergration, the VLSI Journal, 21(1–2):1–94, 1996.

    Article  Google Scholar 

  30. J. Cong, A.B. Kahng, and K.S. Leung. Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. on Computer-Aided Design, 17(1):24–39, Jan. 1999.

    Article  Google Scholar 

  31. A.E. Caldwell, A.B. Kahng, and I.L. Markov. Can recursive bisection produce routable placements? In Proc. 37th IEEE/ACM Design Automation Conf., pages 477–482, 2000.

    Google Scholar 

  32. J. Cong and S.K. Lim. Edge separability based circuit clustering with application to circuit partitioning. In Asia South Pacific Design Automation Conference, Yokohama Japan, pages 429–434, 2000.

    Google Scholar 

  33. Y. Chang and S. Lin. Mr: A new framework for multilevel full-chip routing. IEEE Trans. on Computer Aided Design, 23(5), May 2004.

    Google Scholar 

  34. R.C. Carden, J. Li, and C.K. Cheng. A global router with a theoretical bound on the optimal solution. IEEE Trans. Computer-Aided Design, 15(2):208–216, Feb. 1996.

    Article  Google Scholar 

  35. J. Cong, H. Li, and C. Wu. Simultaneous circuit partitioning/clustering with retiming for performance optimization. Proc. 36th ACM/IEEE Design Automation Conf., pages 460–465, Jun 1999.

    Google Scholar 

  36. J. Cong, S.K. Lim, and C. Wu. Performance-driven multi-level and multiway partitioning with retiming. In Proceedings of Design Automation Conference, pages 274–279, Los Angeles, California, Jun 2000.

    Google Scholar 

  37. J. Cong and P. Madden. Performance driven multi-layer general area routing for PCB/MCM designs. In Proc. 35th Design Automation Conference, pages 356–361, Jun 1998.

    Google Scholar 

  38. H.R. Charney and D.L. Plato. Efficient partitioning of components. In In Proc. of the 5th Annual Design Automation Workshop, pages 16-0–16-21, 1968.

    Google Scholar 

  39. J. Cong and M. Smith. A parallel bottom-up clustering algorithm with applications to circuit partitioning in vlsi designs. In Proc. Design Automation Conference, pages 755–760, San Jose, CA, 1993.

    Google Scholar 

  40. J. Cong and J.R. Shinnerl, editors. Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, Boston, 2003.

    Google Scholar 

  41. J. Cong and C. Wu. Global clustering-based performance-driven circuit partitioning. In Proc. Int. Symp. on Physical Design, pages 149–154, 2002.

    Google Scholar 

  42. B. Choi, H. Xu, M. Wang, and M. Sarrafzadeh. Flow-based cell moving algorithm for desired cell distribution. Proc. IEEE International Conference on Computer Design, pages 218–225, Oct 2003.

    Google Scholar 

  43. J. Cong, M. Xie, and Y. Zhang. An enhanced multilevel routing system. IEEE International Conference on Computer Aided Design, pages 51–58, 2002.

    Google Scholar 

  44. J. Cong and X. Yuan. Routing tree construction under fixed buffer locations. In Proc. 37th Design Automation Conference, pages 379–384, Jun. 2000.

    Google Scholar 

  45. Shantanu Dutt and Wenyong Deng. Vlsi circuit partitioning by cluster-removal using iterative improvement techniques. In Proc. Int’l Conf. on Computer-Aided Design, pages 194–200, 1997.

    Google Scholar 

  46. E.W. Dijkstra. A note on two problems in connexion with graphs. Numerische Mathematik, 1:269–271, 1959.

    Article  MATH  MathSciNet  Google Scholar 

  47. G. DiMicheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, 1994.

    Google Scholar 

  48. W. E. Donath. Logic partitioning. Physical Design Automation in VLSI systems, 1988.

    Google Scholar 

  49. H. Eisenmann and F.M. Johannes. Generic global placement and floor-planning. In Proc. 35th ACM/IEEE Design Automation Conference, pages 269–274, 1998.

    Google Scholar 

  50. C. M. Fiduccia and R. M. Mattheyses. A linear-time heuristic for improving network partitions. In Proc. Design Automation Conference, pages 175–181, 1982.

    Google Scholar 

  51. N. Garg and J. Konemann. Faster and simpler algorithms for multi-commodity flow and other fractional packing problems. In Proc. Annual Symposium on Foundations of Computer Science, pages 300–309, Nov. 1998.

    Google Scholar 

  52. P.E. Gill, W. Murray, and M.H. Wright. Practical Optimization. Academic Press, London and New York, 1981. ISBN 0-12-283952-8.

    Google Scholar 

  53. R. Goering. FPGA placement performs poorly, study says. EE Times, 2003. http://www.eedesign.com/story/OEG20031113S0048.

    Google Scholar 

  54. R. Goering. IC placement benchmarks needed, researchers say. EE Times, 2003. http://www.eedesign.com/story/OEG20030410S0029.

    Google Scholar 

  55. R. Goering. Placement tools criticized for hampering IC designs. EE Times, 2003. http://www.eedesign.com/story/OEG20030205S0014.

    Google Scholar 

  56. S. Goto. An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. on Circuits and Systems, 28(1):12–18, January 1981.

    Article  MathSciNet  Google Scholar 

  57. F. Hadlock. Finding a maximum out of a planar graph in polynomial time. SIAM Journal of Computing, 4(3):221–225, Sep. 1975.

    Article  MATH  MathSciNet  Google Scholar 

  58. D.W. Hightower. A solution to line routing problems on the continuous plane. In Proc. IEEE 6th Design Automation Workshop, pages 1–24, 1969.

    Google Scholar 

  59. D. Hill. Method and system for high speed detailed placement of cells within an integrated circuit design. In US Patent 6370673, Apr 2002.

    Google Scholar 

  60. M. Hannan and J.M. Kurtzberg. A review of the placement and quadratic assignment problems. SIMA, 14, 1972.

    Google Scholar 

  61. J. Heisterman and T. Lengauer. The efficient solution of integer programs for hierarchical global routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(6):748–753, Jun. 1991.

    Article  Google Scholar 

  62. S.-W. Hur and J. Lillis. Relaxation and clustering in a local search framework: Application to linear placement. In Proc. ACM/IEEE Design Automation Conference, pages 360–366, New Orleans, LA, Jun 1999.

    Google Scholar 

  63. S.-W. Hur and J. Lillis. Mongrel: Hybrid techniques for standard-cell placement. In Proc. IEEE International Conference on Computer Aided Design, pages 165–170, San Jose, CA, Nov 2000.

    Google Scholar 

  64. B. Hu and M. Marek-Sadowska. Fine granularity clustering for largescale placement problems. In Proc. Int’l Symp. on Physical Design, Apr. 2003.

    Google Scholar 

  65. B. Hu and M. Marek-Sadowska. Wire length prediction based clustering and its application in placement. In Proc. Design Automation Conference, Jun. 2003.

    Google Scholar 

  66. B. Hu and M. Marek-Sadowska. Fine granularity clustering based placement. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Apr. 2004.

    Google Scholar 

  67. M. Hayashi and S. Tsukiyama. A hybrid hierarchical approach for multilayer global routing. Proceedings of the 1995 European conference on Design and Test, pages 492–496, Mar. 1995.

    Google Scholar 

  68. International Technology Roadmap for Semiconductors. http://public.itrs.net/.

    Google Scholar 

  69. M. Romesis J. Cong and M. Xie. Optimality, scalability and stability study of partitioning and placement algorithms. In Proc. International Symposium on Physical Design, 2003.

    Google Scholar 

  70. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Application in VLSI domain. In Proc. 34th ACM/IEEE Design Automation Conference, pages 526–529, 1997.

    Google Scholar 

  71. G. Karypis. Multilevel algorithms for multi-constraint hypergraph partitioning. Technical Report 99-034, Department of Computer Science, University of Minnesota, Minneapolis, 1999.

    Google Scholar 

  72. G. Karypis. Multilevel Hypergraph Partitioning, chapter 3 of Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, 2002.

    Google Scholar 

  73. R.M. Karp, F.T. Leighton, R.L. Rivest, C.D. Thompson, U.V. Vazirani, and V. V. Vazirani. Global wire routing in two-dimensional arrays. Algorithmica, 2:113–129, 1987.

    Article  MathSciNet  Google Scholar 

  74. J.M. Kleinhans, G. Sigl, F.M. Johannes, and K.J. Antreich. Gordian: VLSI placement by quadratic programming and slicing optimization. IEEE Trans. on Computer-Aided Design, 10:356–365, 1991.

    Article  Google Scholar 

  75. A.B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. In Proc. Int’l Symp. on Physical Design, pages 18–25, 2004.

    Google Scholar 

  76. Y. Lin, Y. Hsu, and F. Tsai. Hybrid routing. IEEE Transactions on Computer-Aided Design, 9(2):151–157, Feb. 1990.

    Article  Google Scholar 

  77. J. Li, J. Lillis, and C. Cheng. Linear decomposition algorithm for vlsi design applications. In Proc. Int’l Conf. on Computer-Aided Design, pages 223–228, 1995.

    Google Scholar 

  78. J. Lou, S. Thakur, S. Krishnamoorthy, and H. Sheng. Estimating routing congestion using probabilistic analysis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21(1):32–41, January 2002.

    Article  Google Scholar 

  79. L. McMurchie and C. Ebeling. Pathfinder: a negotiation-based performance-driven router for FPGAs. In Proc, of ACM Symposium on Field-Programmable Gate Array, pages 111–117, Feb. 1995.

    Google Scholar 

  80. K. Mikami and K. Tabuchi. A computer program for optimal routing of printed ciurcuit connectors. IFIPS Proc, H-47:1475–1478, 1968.

    Google Scholar 

  81. R. Nair. A simple yet effective technique for global wiring. IEEE Trans. on Computer-Aided Design, 6(2), 1987.

    Google Scholar 

  82. S.G. Nash and A. Sofer. Linear and Nonlinear Programming. McGraw Hill, New York, 1996.

    Google Scholar 

  83. N. Quinn and M. Breuer. A force-directed component placement procedure for printed circuit boards. IEEE Trans. on Circuits and Systems GAS, CAS-26:377–388, 1979.

    Article  Google Scholar 

  84. Bernhard M. Riess, Konrad Doll, and Frank M. Johannes. Partitioning very large circuits using analytical placement techniques. In Proc. Design Automation Conference, pages 646–651, 1994.

    Google Scholar 

  85. G. Sigl, K. Doll, and F.M. Johannes. Analytical placement: A linear or a quadratic objective function? In Proc. 28th ACM/IEEE Design Automation Conference, pages 427–432, 1991.

    Google Scholar 

  86. Naveed Sherwani. Algorithms for VLSI Physical Design Automation. Kluwer Academic Publishers, Boston, Dordrecht, London, third edition, 1999.

    Google Scholar 

  87. J. Soukup. Fast maze router. In Proc. 15th Design Automation Conference, pages 100–102, 1978.

    Google Scholar 

  88. Y. Sankar and J. Rose. Trading quality for compile time: Ultra-fast placement for FPGAs. In FPGA’ 99, ACM Symp. on FPGAs, pages 157–166, 1999.

    Google Scholar 

  89. W.-J. Sun and C. Sechen. Efficient and effective placement for very large circuits. IEEE Trans. on Computer-Aided Design, pages 349–359, Mar 1995.

    Google Scholar 

  90. M. Sarrafzadeh, M. Wang, and X. Yang. Modern Placement Techiques. Kluwer Academic Publishers, Boston, 2002.

    Google Scholar 

  91. U. Trottenberg, C.W. Oosterlee, and A. Schüller. Multigrid. Academic Press, London, 2000.

    Google Scholar 

  92. Jens Vygen. Algorithms for large-scale flat placement. In Proc. 34th ACM/IEEE Design Automation Conference, pages 746–751, 1997.

    Google Scholar 

  93. Dongsheng Wang and E.S Kuh. A new timing-driven multilayer mcm/ic routing algorithm. In Proc. IEEE Multi-Chip Module Conference, pages 89–94, Feb. 1997.

    Google Scholar 

  94. M. Wang, X. Yang, and M. Sarrafzadeh. Dragon2000: Standard-cell placement tool for large industry circuits. In Proc. International Conference on Computer-Aided Design, pages 260–264, 2000.

    Google Scholar 

  95. M. Wang, X. Yang, and M. Sarrafzadeh. Dragon2000: Standard-cell placement tool for large circuits. Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 260–263, Apr 2000.

    Google Scholar 

  96. H. Xu, M. Wang, B. Choi, and M. Sarrafzadeh. A trade-off oriented placement tool. Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 467–471, Apr 2003.

    Google Scholar 

  97. M.C. Yildiz and P.H. Madden. Improved cut sequences for partitioning-based placement. In Proc. Design Automation Conference, pages 776–779, 2001.

    Google Scholar 

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Authors and Affiliations

  1. UCLA Mathematics Department, Los Angeles, California, 90095-1555, USA

    Tony F. Chan & Kenton Sze

  2. UCLA Computer Science Department, Los Angeles, California, 90095-1596, USA

    Jason Cong, Joseph R. Shinnerl, Min Xie & Yan Zhang

Authors
  1. Tony F. Chan
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  2. Jason Cong
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  3. Joseph R. Shinnerl
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  4. Kenton Sze
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  5. Min Xie
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  6. Yan Zhang
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Editor information

Editors and Affiliations

  1. University of Florida, Gainesville, Florida

    William W. Hager , Shu-Jen Huang , Panos M. Pardalos  & Oleg A. Prokopyev , ,  & 

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Chan, T.F., Cong, J., Shinnerl, J.R., Sze, K., Xie, M., Zhang, Y. (2006). Multiscale Optimization in VLSI Physical Design Automation. In: Hager, W.W., Huang, SJ., Pardalos, P.M., Prokopyev, O.A. (eds) Multiscale Optimization Methods and Applications. Nonconvex Optimization and Its Applications, vol 82. Springer, Boston, MA. https://doi.org/10.1007/0-387-29550-X_1

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