Skip to main content

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 27))

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. International Technolog y Roadmap for Semiconductors, 2003 Edition, http://public.itrs.net/Files/2003ITRS/Home2003.htm

  2. R. D. Adams, High Performance Memory Testing: Design Principles, Fault modeling, and Self-Test, Kluwer, 2002, ISBN 1402072554.

    Google Scholar 

  3. T. Barnett, A. Singh, “Relating yield models to burn-in fall-out in time, ” IEEE International Test Conference 2003, pp. 77-84.

    Google Scholar 

  4. S. Subramanian, et al., “A practical experience of implementing memory repair in COT,” IEEE VLSI Test Symposium 2004, presentation.

    Google Scholar 

  5. M. Kume, et al., “Programmable at-speed array and functional BIST for embedded DRAM LSI,” IEEE International Test Conference 2004, pp. 988-96.

    Google Scholar 

  6. R. D. Adams, et al., “An integrated memory self test and EDA solution, ” IEEE Memory, Technology Design, and Test Workshop 2004, pp. 92-5.

    Google Scholar 

  7. M. Ouellette, et al., “On-chip repair and an ATE independent fusing methodology, ” IEEE International Test Conference 2002, pp. 178-86.

    Google Scholar 

  8. M. Mohammad, K. K. Saluja, “Flash memory disturbances: modeling and test, ” IEEE VLSI Test Symposium 2001, pp. 218-24.

    Google Scholar 

  9. K. Bernstein, N. Rohrer, SOI Circuit Design Concepts, Kluwer, 2000, ISBN 0792377621.

    Google Scholar 

  10. K. Osada, “Universal-VDD 0. 65-2. 0 V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell, ” IEEE Journal of Solid-State Circuits Vol. 36, No. 11, 11/2001, pp. 1738-43.

    Article  Google Scholar 

  11. H. Pilo, R. D. Adams, et al., “Bitline Contacts in High-Density SRAMS: design for testability and stressability, ” IEEE International Test Conference 2001, pp. 776-82.

    Google Scholar 

  12. H. Miyatake, M. Tanaka, Y. Mori, “A design for high-speed low-power CMOS fully parallel content-addressable memory macros, ” IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, 6/2001, pp. 956-68.

    Article  Google Scholar 

  13. H. Kimura, et al., “Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI, ” IEEE Journal of Solid-State Circuits Vol. 39, No. 6, 6/2004, pp. 919-26.

    Article  Google Scholar 

  14. V. Lines, et al., “66MHz 2. 3M ternary dynamic content addressable memory, ” IEEE Memory Technology, Design, and Test Workshop 2000, pp. 101-5.

    Google Scholar 

  15. L. Dilillo, et al., “Data retention fault in SRAM memories: Analysis and detection procedures, ” IEEE VLSI Test Symposium 2005, pp. 218-24.

    Google Scholar 

  16. P. Pavan, L. Larcher, A. Marmiroli, Floating Gate Devices: Operation and Compact Modeling, Kluwer, 2003, ISBN 1402077319.

    Google Scholar 

  17. Z. Al-Ars, et al., “Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs, ” IEEE International Test Conference 2002, pp. 783-92.

    Google Scholar 

  18. R. D. Adams, E. S. Cooley, “Analysis of a deceptive destructive read memory fault model and recommended testing, ” IEEE North Atlantic Test Workshop 1996, pp. 27-32.

    Google Scholar 

  19. J. Brauch, J. Fleischman, “Design of cache test hardware on the HP PA8500, ” IEEE International Test Conference 1997, pp. 286-93.

    Google Scholar 

  20. S. Hamdioui, Testing Static Random Access Memories, Kluwer, 2004, ISBN 1402077521.

    MATH  Google Scholar 

  21. J. Zhao, et al., “Detection of inter-port faults in multi-port static RAMs, ” IEEE VLSI Test Symposium 2000, pp. 297-302.

    Google Scholar 

  22. S. Hamdioui, “Testing multi-port memories: Theory and practice, ” Ph. D. Dissertation, Delft University, 2001.

    Google Scholar 

  23. R. Gibbins, R. D.Adams, et al., “Design and test of a 9-port SRAM for a 100Gb/s STS-1 switch, ” IEEE Memory Technology, Design, and Test Workshop 2002.

    Google Scholar 

  24. A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, ComTex Publishing, Gouda, The Netherlands, 1998, ISBN 9080427616.

    Google Scholar 

  25. A. J. van de Goor, I. B. S. Tlili, “March tests for word-oriented memories, ” IEEE Design, Automation and Test in Europe Conference 1998, pp. 501-8.

    Google Scholar 

  26. A. J. van de Goor, S. Hamdioui, R. Wadsworth, “Detecting faults in the peripheral circuits and an evalution of SRAM tests, ” IEEE International Test Conference 2004, pp. 114-23.

    Google Scholar 

  27. A. J. van de Goor, et al., “March LR: A test for realistic linked faults, ” IEEE VLSI Test Symposium 1996, pp. 272-80.

    Google Scholar 

  28. A. J. van de Goor, “Using march tests to test SRAMs, ” IEEE Design & Test of Computers, 3/1993, pp. 8-13.

    Google Scholar 

  29. K. Lin, C. Wu, “Functional testing of content-addressable memories, ” IEEE Memory Technology, Design, and Test Workshop 1998, pp. 70-5.

    Google Scholar 

  30. P. H. Bardell, W. H. McAnney, J. Savir, Built-In Test for VLSI, Wiley, 1987, ISBN 0471624632.

    Google Scholar 

  31. C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Kluwer Academic Publishers, 2002, ISBN 1402070500.

    Google Scholar 

  32. E. MacDonald, N. A. Touba, “Delay testing of SOI circuits: Challenges with the history effect, ” IEEE International Test Conference 1999, pp. 269-75.

    Google Scholar 

  33. R. D. Adams, P. Shephard III, “Silicon on insulator technology impacts on SRAM testing, ” IEEE VLSI Test Symposium 2000, pp. 43-47.

    Google Scholar 

  34. G. Braun, et al., “A robust 8F2 ferroelectric RAM cell with depletion device (DeFeRAM), ” IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, 5/2000, pp. 691-6.

    Article  Google Scholar 

  35. S. Tehrani, et al., “Progress and outlook for MRAM technology, ” IEEE Transactions on Magnetics, Vol. 35, No. 5, 9/1999, pp. 2814-9.

    Article  Google Scholar 

  36. M. Gill, T. Lowrey, J. Park, “Ovonic unified memory -a high-performance nonvolatile memory technology for stand-alone memory and embedded applications, ” IEEE International Solid State Circuits Conference 2002, pp. 202-3.

    Google Scholar 

  37. C. L. Su, R. F. Huang, C. W. Wu, “MRAM defect analysis and fault modeling, ” IEEE International Test Conference 2004, pp. 124-133.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer

About this chapter

Cite this chapter

Adams, R.D. (2006). Embedded MemoryTesting. In: Gizopoulos, D. (eds) Gizopoulos / Advances in ElectronicTesting. Frontiers in Electronic Testing, vol 27. Springer, Boston, MA. https://doi.org/10.1007/0-387-29409-0_8

Download citation

  • DOI: https://doi.org/10.1007/0-387-29409-0_8

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-29408-7

  • Online ISBN: 978-0-387-29409-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics