Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Segura and C. Hawkins, CMOS Electronics: How it Works, How it Fails, IEEE Press -John Wiley & Sons, NJ, 2004. ISBN0-471-47669-2.
A. Keshavarzi, C. Hawkins and K. Roy, “Intrinsic leakage in low-power deep submicron ICs”, IEEE Int. Test Conference, pp. 147-158, 1997.
S. Thompson, et. al., “130 nm logic technology featuring 60 nm transistors, low-K dielectrics, and Cu interconnects”, Intel Technology Journal, vol. 6, no. 2, pp. 5-13, 2002.
Y. Taur, “CMOS design near the limit of scaling” IBM Journal of Research & Development, vol. 46, no. 2/3, March/May 2002.
S. T. Ma, A. Keshavarzi, V. De, and J. R. Brews “A Statistical Model for Extracting Geometric Sources of Transistor Performance Variation”, IEEE Tran Electron Devices, vol. 51, no. 1, pp. 36-41, January 2004.
W. Abadeer and W. Ellis, “Behavior of NBTI under ac dynamic circuit conditions, ” International Reliability Physics Symposium (IRPS), pp. 17-22, April 2003.
N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance” IEEE Tran Electron Devices, vol. 49, no. 51, pp. 826-831, May 2002.
W. Grobman, et. al., “Reticle enhancement technology: implications and challenges for physical design, ” Design Automation Conference, June 2001.
V. Mehrotra and D. Boning, “Technology scaling impact of variation on clock skew and interconnect delay, ” IEEE Int. Interconect Technology Conference, pp. 122-124, 2001.
S. Natarajan, M. Breuer and S. Gupta, “Process variations and their impact on circuit operation, ” International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 73-81, November 1998.
J. Segura, A. Keshavarzi, J. Soden, and C. Hawkins, “Parametric failures in CMOS ICs -A defect-based analysis, ” IEEE International Test Conference (ITC), pp. 90-99, October 2002.
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De “Parameter Variations and Impact on Circuits and Microarchitecture” Design Automation Conference (DAC), pp. 338-342, 2003.
S. Bota, M. Rosales, J. L. Roselló, A. Keshavarzi and J. Segura “Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism” IEEE Int. Test Conference, 2004.
A. Deutsch, et al., “On-chip wiring design challenges for gigahertz operation,” Proceeding of the IEEE, Vol. 89, No. 4, April 2001.
J. Segura, V. Champac, R. Rodríguez, J. Figueras, and A. Rubio, “Quiescent current analysis and experimentation of defective CMOS circuits, ” Journal of Electronic Testing: Theory and Applications, Vol 3, pp. 337-348, 1992.
C. Hawkins, J. Soden, A. Righter, and J. Ferguson, “Defect classes -An overdue paradigm for testing CMOS ICs, ” IEEE International Test Conference (ITC), pp. 413-424, October 1994.
R. Wadsack, “Fault modeling and logic simulation of CMOS and MOS integrated circuits, ” Bell Systems Technical Journal, pp. 1449-1488, May-June 1978.
J. Soden, R. Treece, M. Taylor, and C. Hawkins, “CMOS IC stuck-open fault electrical effects and design considerations, ” pp. 423-430, International Test Conference (ITC), pp. 302-310, August 1989.
T. Turner, “A step-by-step method for elimination of burn-in as a necessary screen, ” 96IRM Final Report, pp. 82-86, 1997.
J. S. Suehle, “Ultra-Thin gate Oxide Breakdown: A Failure that we can live with?” Electronic Device Failure Analysis, Vol. 6, No. 1, pp. 6-11, February 2004.
J. Segura, C. De Benito, A. Rubio, and C. Hawkins, “A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level, ” IEEE International Test Conference (ITC), pp. 544-550, October 1995.
R. Degraeve, B. Kaczer, A. De Keersgieter, and G. Groeseneken, “Relation Between Breakdown Mode and breakdown Location in Short Channel NMOSFETs, ” International Reliability Physics Symposium (IRPS), pp. 360-366, May 2001.
A. Gattiker and W. Maly, “Current signatures: application, ” IEEE International Test Conference (ITC), pp. 156-165, 1997.
C. Thibeault, “An histogram based procedure for current testing of active defects, ” International Test Conference (ITC), pp. 714-723, October 1999.
A. Miller, “IDDQ testing in deep submicron integrated circuits, ” International Test Conference (ITC), pp. 724-729, October 1999.
P. Maxwell, P. O’Neill, R. Aitken, R. Dudley, N. Jaarsma, M. Quach, and D. Wiseman, “Current ratios: A self-scaling technique for production IDDQ testing, ” International Test Conference (ITC), pp. 738-746, October 1999.
R. Daasch, K. Cota, J. McNames, and R. Madge, “Neighbor selection for variance reduction in IDDQ and other parametric data, ” International Test Conference (ITC), October 2001.
A. Keshavarzi, K. Roy, M. Sachdev, C. Hawkins, K. Soumyanath, and V. De, “Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ, ” IEEE International Test Conference (ITC), pp. 1051-1059, October 2000.
H. Hao and E. McCluskey, “Very-low voltage testing for weak CMOS logic ICs, ” IEEE International Test Conference, pp. 275-284, 1993.
R. Madge, B. Goh, V. Rajagopalan, C. Macchietto, R. Daasch, C. Shuermyer, C. Taylor, and D. Turner, “Screening MinVDD outliers using feed-foward voltage testing analysis, ” IEEE International Test Conference (ITC), pp. 673-682, 2002.
T. M. Mak, A. Krstic, K. T. Cheng, and Li-C. Wang, “New challenges in delay test of nanometer multigigaherts designs” IEEE Design & Test of Computers, pp. 241-247, May-June 2004.
J-J. Liou, A. Krstic, Y-M. Jiang, and K-T. Cheng, “Modeling, Testing, and Analysis for Delay Defects and Noise Effects in Deep Submicron Devices” IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 756-769, June 2003.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer
About this chapter
Cite this chapter
Segura, J., Hawkins, C., Soden, J. (2006). Failure Mechanisms and Testing in Nanometer Technologies. In: Gizopoulos, D. (eds) Gizopoulos / Advances in ElectronicTesting. Frontiers in Electronic Testing, vol 27. Springer, Boston, MA. https://doi.org/10.1007/0-387-29409-0_2
Download citation
DOI: https://doi.org/10.1007/0-387-29409-0_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-29408-7
Online ISBN: 978-0-387-29409-4
eBook Packages: EngineeringEngineering (R0)