Skip to main content
SpringerLink
Log in

Defect-Orinted Testing

  • Chapter
Book cover Gizopoulos / Advances in ElectronicTesting

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 27))

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive Fault Analysis of MOS Integrated Circuits, ” IEEE Design and Test, Vol. 2, No. 6, pp. 13-36, Dec. 1985.

    Article  Google Scholar 

  2. R. Rodriguez-Montanes, E. Bruls, and J. Figueras, “Bridging Defects Resistance Measurements in a CMOS Process”, Proc. IEEE International Test Conf., pp. 892-896, 1992.

    Google Scholar 

  3. R. C. Aitken, “New Defect Behavior at 130nm and Beyond”, European Test Symposium, May 2004.

    Google Scholar 

  4. M. Tripp, comments at Defect Based Testing Workshop, Monterey, CA, April 2001.

    Google Scholar 

  5. R. Rodrigues-Montanes, P. Volf, J. Pineda de Gyvez, “Resistance Characterization for Weak Open Defects”, IEEE Design and Test, Vol. 19, No. 5, pp. 18-26, Sept. -Oct. 2002.

    Article  Google Scholar 

  6. W. Maly et al, “Deformations of IC Structure in Test and Yield Learning”, Proc. IEEE International Test Conference, pp. 856-865, 2003.

    Google Scholar 

  7. F M. Schellenberg, “Sub-Wavelength Lithography Using OPC”, Semiconductor Fabtech Journal, 9th edition, March 1999.

    Google Scholar 

  8. C. Guardiani et al, “Proactive Design For Manufacturing (DFM) for Nanometer SoC Designs”, Proc. IEEE Custom Int. Circ. Conf., pp. 309-316, 2004.

    Google Scholar 

  9. L. Wei, Z Chen, M. Johnson, K. Roy and V. De, “Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits”, Proc. ACM/IEEE Design Automation Conf., pp. 489-494, 1998.

    Google Scholar 

  10. R. Aitken et al, “Library Modeling for Effective Leakage Management”, Proc. Synopsys Users Group, San Jose CA, 2004.

    Google Scholar 

  11. J. Segura, C. F. Hawkins, CMOS Electronics: How It Works, How It Fails, IEEE Press (Wiley), 2004.

    Google Scholar 

  12. D. Monticelli, “Solving the Real Challenges of Low-Power SOC Design in90 Nanometers”, DesignCon 2004, Santa Clara CA, February 2004.

    Google Scholar 

  13. J. Dworak et al, “Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation -MPG-D”, Proc. IEEE International Test Conference, pp. 930-939, 2000.

    Google Scholar 

  14. R. D. Eldred, “Test Routines Based on Symbolic Logical Statements, ” Journal of the ACM, Vol. 6, pp. 33-36, 1959.

    Article  MATH  MathSciNet  Google Scholar 

  15. M. R. Grimaila et al, “REDO -Random Excitation and Deterministic Observation -First Commercial Experiment”, Proc. IEEE VLSI Test Symposium, pp. 268-274, Apr. 1999.

    Google Scholar 

  16. K. C. Y. Mei, “Bridging and Stuck-at Faults, ” IEEE Trans. Computers, Vol. C-23, pp. 720-727, July 1974.

    Google Scholar 

  17. I. Polian, On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications. VDI Fortschritt-Berichte, Reihe 20, Nr. 377. VDI-Verlag, Düsseldorf. 2004.

    Google Scholar 

  18. J. M. Acken, S. D. Millman, “Accurate Modeling and Simulation of Bridging Faults”, Proc. IEEE Custom Integrated Circuits Conference, pp. 17. 4. 1-17. 4. 4, 1991.

    Google Scholar 

  19. P. C. Maxwell and R. C. Aitken, “Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds”, Proc. IEEE International. Test Conf., pp. 63-72, 1993.

    Google Scholar 

  20. R. L. Wadsack, “Fault Modelling and Logic Simulation of CMOS and MOS Integrated Circuits, ” Bell Sys. Tech. Jour., Vol. 57, pp. 1449-1474, 1978.

    Google Scholar 

  21. T. W. Williams et al, “The Interdependence Between Delay-Optimization of Synthesized Networks and Testing”, Proc. ACM/IEEE Design Automation Conf., pp. 87-92, 1991.

    Google Scholar 

  22. S. Chakravarty and P. Thadikaran, Introduction to IDDQ Testing, Kluwer Academic Publishers, 1997.

    Google Scholar 

  23. T. W. Williams et al, “Iddq Test: Sensitivity Analysis of Scaling”, Proc. IEEE International Test Conf., pp. 786-792, Washington DC, Oct. 1996.

    Google Scholar 

  24. R. C. Aitken “Finding Defects with Fault Models”, Proc. IEEE International Test Conf. pp. 498-505, 1995.

    Google Scholar 

  25. D. Josephson, M. Storey, and D. Dixon, “Microprocessor IDDQ Testing: A Case Study”, IEEE Design and Test, Vol. 12, No. 2, pp. 42-52, Summer 1995.

    Article  Google Scholar 

  26. P. Nigh et al, “An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDq and Delay Fault Testing”, Proc. VLSI Test Symp., pp. 459-464, 1997.

    Google Scholar 

  27. P. Maxwell et al, “Current Ratios: A Self-Scaling Technique for Production IDDQ Testing”, Proc. IEEE International Test Conf., pp. 738-746, 1999.

    Google Scholar 

  28. E. Peterson and W. Jiang, “Practical Application of Energy Consumption Ratio Test”, Proc. IEEE International Test Conf., pp. 386-394, 2001.

    Google Scholar 

  29. J. Rearick and M. Sharma, “Method and apparatus for measuring the quality of delay test patterns”, U. S. Patent #6708139, 2004.

    Google Scholar 

  30. T. McLaurin, “Debugging and Diagnosing Delay Defects in Deep Submicron Designs”, Proc. Silicon Debug and Diagnosis Workshop, 2004.

    Google Scholar 

  31. P. Maxwell, I. Hartanto, and L. Bentz, “Comparing Functional and Structural Tests”, Proc. IEEE International Test Conf., pp. 400-407, 2000.

    Google Scholar 

  32. J. T. Y. Chang and E. J. McCluskey, “Detecting Delay Flaws by Very Low Voltage Testing”, Proc. IEEE International Test Conf., pp. 367-376, 1996.

    Google Scholar 

  33. R. Madge, B. Goh, V. Rajagopalan, “Screening Min VDD Outliers Using Feed-Forward Voltage Testing”, Proc. IEEE International Test Conf., pp. 673-682, 2002.

    Google Scholar 

  34. R. C. Aitken, “Test Generation and Fault Modeling for Stress Testing”, Proc. Int. Symp. on Quality in Elect. Design, pp. 95-99, 2002.

    Google Scholar 

  35. A. Righter, “IDDQ/Burn-in Effectiveness, ” SEMATECH Project Report S-88B, January 1997.

    Google Scholar 

  36. P. C. Maxwell, R. C. Aitken, V. Johansen, and I. Chiang, “The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90%”, Proc. IEEE International Test Conf., pp. 358-364, 1991.

    Google Scholar 

  37. P. C. Maxwell, R. C. Aitken, “The Effectiveness of IDDQ, Functional, and Scan Tests: How Many Fault Coverages Do We Need?”, Proc. IEEE International Test Conf., pp. 168-177, 1992.

    Google Scholar 

  38. P. C. Maxwell, R. C. Aitken, K. R. Kollitz, and A. C. Brown, “IDDQ and AC Scan: The War Against Unmodeled Defects”, Proc. IEEE International Test Conf., pp. 250-258, 1996.

    Google Scholar 

  39. P. Nigh et al, “An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDq and Delay Fault Testing”, Proc. IEEE VLSI Test Symp., pp. 459-464, April 1997.

    Google Scholar 

  40. P. Nigh et al, “Failure Analysis of Timing and Iddq-Only Failures from the SEMATECH Test Methods Experiment”, Proc. IEEE International Test Conf., pp. 43-52 Nov. 1998.

    Google Scholar 

  41. C. Thibeault, “Speeding-up IDDQ Measurements”, Proc. IEEE VLSI Test Symposium, pp. 295-301, 2002.

    Google Scholar 

  42. W. Daasch et al, “Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data”, Proc. IEEE International Test Conf., pp. 92-100, 2001.

    Google Scholar 

  43. R. Madge et al, “Screening MinVDD Outliers Using Feed-Forward Voltage Testing”, Proc. IEEE International Test Conf., pp. 673-682, 2002.

    Google Scholar 

  44. T. W. Williams et al, “Iddq Test: Sensitivity Analysis of Scaling”, Proc. IEEE International Test Conf., pp. 786-792, 1996.

    Google Scholar 

  45. C. Visweswariah, “Death, Taxes, and Failing Chips”, Proc. Design Automation Conf., pp. 343-347, 2003.

    Google Scholar 

  46. D. Ernst et al, “Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation”, IEEE Micro, 24(6):10-20, November 2004.

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Physical IP, ARM, Inc., Sunnyvale, CA, USA

    Robert C Aitken

Authors
  1. Robert C Aitken
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. University of Piraeus, Greece

    Dimitris Gizopoulos

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer

About this chapter

Cite this chapter

Aitken, R.C. (2006). Defect-Orinted Testing. In: Gizopoulos, D. (eds) Gizopoulos / Advances in ElectronicTesting. Frontiers in Electronic Testing, vol 27. Springer, Boston, MA. https://doi.org/10.1007/0-387-29409-0_1

Download citation

  • DOI: https://doi.org/10.1007/0-387-29409-0_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-29408-7

  • Online ISBN: 978-0-387-29409-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation