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FPGA Implementations of Neocognitrons

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Book cover FPGA Implementations of Neural Networks

Abstract

In this chapter it is described the implementation of an artificial neural network in a reconfigurable parallel computer architecture using FPGA’s, named Reconfigurable Orthogonal Memory Multiprocessor (REOMP), which uses p 2 memory modules connected to p reconfigurable processors, in row access mode, and column access mode. It is described an alternative model of the neural network Neocognitron; the REOMP architecture, and the case study of alternative Neocognitron mapping; the performance analysis considering the computer systems varying the number of processors from 1 to 64; the applications; and the conclusions.

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References

  1. Arantes, M., Ide, A. N., and Saito, J. H. A System for Fingerprint Minutiae Classification and Recognition. volume 5, pages 2474–2478. Proceedings of the 9th International Conference on Neural Information Processing-ICONIP’2002. Singapura, 2002.

    Google Scholar 

  2. Bianchini, A. R. Arquitetura de Redes Neurais para o Reconhecimento Facial Baseado no Neocognitron. Master’s thesis, Universidade Federal de São Carlos.

    Google Scholar 

  3. T. J. Callahan, J. R. Hauser, and J. Wawrzyneck. The Garp Architecture and C Compiler. volume 33, pages 62–69. IEEE Computer Society, Computer: Innovative Technology for Computer Professionals, April 2002.

    Google Scholar 

  4. A. Dehon. Reconfigurable Architecture for General Purpose Computing. PhD thesis, Massachussets Institute of Technology (MIT), 1996.

    Google Scholar 

  5. A. Dehon. The Density Advantage of Configurable Computing. volume 33. IEEE Computer, 2000.

    Google Scholar 

  6. K. Fukushima. Neural-Network Model for a Mechanism of Pattern Recognition Unaffected by Shift in Position-Neocognitron. volume 62-A. Transactions of the IECE, 1979. Japan.

    Google Scholar 

  7. K. Fukushima and S. Miyake. Neocognitron: A New Algorithm for Pattern Recognition Tolerant of Deformations and Shift in Position. volume 15, pages 455–469. Pattern Recognition, 1982.

    Article  Google Scholar 

  8. K. Fukushima and M. Tanigawa. Use of Different Thresholds in Learning and Recognition. volume 11, pages 1–17. Neurocomputing, 1996.

    Article  Google Scholar 

  9. K. Fukushima and N. Wake. Improved Neocognitron with Bend-D detecting Cells. Proceedings of the IEEE-International Joint Conference on Neural Networks, 1992. Baltimore, Maryland.

    Google Scholar 

  10. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R. R. Taylor. Piperench: A Reconfigurable Architecture and Compiler. volume 33, pages 70–77, Issue 4. IEEE Computer, April 2000.

    Google Scholar 

  11. S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. Piperench: A Coprocessor for Streaming Multimedia Acceleration. pages 28–39. Proceedings of the 26th. Annual International Symposium on Computer Architecture (ISCA’99), 1999.

    Google Scholar 

  12. S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. The Chimaera Reconfigurable Functional Unit. pages 87–96. Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’97), April 1997.

    Google Scholar 

  13. J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines-FCCM’ 97, April 1997. USA.

    Google Scholar 

  14. D. H. Hubel and T. N.Wiesel. Receptive Fields and Functional Architecture of Monkey Striate Cortex. volume 165, pages 215–243. J. Physiology, 1968.

    Google Scholar 

  15. K. Hwang, P. Tseng, and D. Kim. An Orthogonal Multiprocessor for Parallel Scientific Computations. volume 38, Issue 1, pages 47–61. IEEE Transactions On Computers, January, 1989.

    Article  MATH  Google Scholar 

  16. A. N. Ide and J. H. Saito. A Reconfigurable Computer REOMP. volume 13, pages 62–69. Proceedings of the 13th Symposium on Computer Architecture and High Performance Computing-SBAC-PAD’2001, September 2001. Pirenópolis.

    Google Scholar 

  17. G. Lu. Modeling, Implementation and Scalability of the MorphoSys Dynamically Reconfigurable Computing Architecture. PhD thesis, Electrical and Computer Engineering Department, University of California, 2000. Irvine.

    Google Scholar 

  18. E. A. Mirsky. Coarse-Grain Reconfigurable Computing. PhD thesis, Massachussetts Institute of Technology, June 1996.

    Google Scholar 

  19. J. H. Saito. A Vector Orthogonal Multiprocessor NEOMP and Its Use in Neural Network Mapping. volume 11. Proceedings of the SBACPAD’ 99–11th Symposium on Computer Architecture and High Performance Computing, 1999. Natal, RN, Brazil.

    Google Scholar 

  20. H. Singh. Reconfigurable Architectures for Multimedia and Parallel Application Domains. PhD thesis, Electrical and Computer Engineering Department, University of California, 2000. Irvine.

    Google Scholar 

  21. H. Singh, M. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh, and E. M. C. Filho. Morphosys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. volume 49, pages 465–481. IEEE Transactions on Computers, May 2000.

    Article  Google Scholar 

  22. M. J. Wirthlin and B. I. Hutchings. A Dynamic Instruction Set Computer. Proceedings of the IEEE Symposium on FPGA’s for Custom Computing Machines, April 1995.

    Google Scholar 

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Ide, A.N., Saito, J.H. (2006). FPGA Implementations of Neocognitrons. In: Omondi, A.R., Rajapakse, J.C. (eds) FPGA Implementations of Neural Networks. Springer, Boston, MA . https://doi.org/10.1007/0-387-28487-7_7

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  • DOI: https://doi.org/10.1007/0-387-28487-7_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-28485-9

  • Online ISBN: 978-0-387-28487-3

  • eBook Packages: EngineeringEngineering (R0)

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