Abstract
Associative networks have a number of properties, including a rapid, compute efficient best-match and intrinsic fault tolerance, that make them ideal for many applications. However, large networks can be slow to emulate because of their storage and bandwidth requirements. In this chapter we present a simple but effective model of association and then discuss a performance analysis we have done in implementing this model on a single high-end PC workstation, a PC cluster, and FPGA hardware.
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Hammerstrom, D., Gao, C., Zhu, S., Butts, M. (2006). FPGA Implementation of Very Large Associative Memories. In: Omondi, A.R., Rajapakse, J.C. (eds) FPGA Implementations of Neural Networks. Springer, Boston, MA . https://doi.org/10.1007/0-387-28487-7_6
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DOI: https://doi.org/10.1007/0-387-28487-7_6
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