Abstract
Amethod for analyzing and predicting the timing properties of a program fragment will be described. First an architectural description language implemented to describe a processor’s architecture is presented, followed by the presentation of a new, static worst-case execution time (WCET) estimation method. The timing analysis starts by compiling a processor’s architecture program, followed by the disassembling of the program fragment. After sectioning the assembler program into basic blocks, call graphs are generated and these data are later used to evaluate the pipeline hazards and cache miss that penalize the real-time performance. Some experimental results of using the developed tool to predict the WCET of code segments using some Intel microcontroller are presented. Finally, some conclusions and future work are presented.
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© 2005 Springer Science+Business Media, Inc.
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Tavares, A., Silva, C., Lima, C., Metrolho, J., Couto, C. (2005). WCET Prediction for Embedded Processors Using an ADL. In: Design of Embedded Control Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-28327-7_4
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DOI: https://doi.org/10.1007/0-387-28327-7_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-23630-8
Online ISBN: 978-0-387-28327-2
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