Abstract
The paper presents some hardware solutions for the bit-byte CPU of a PLC, which are oriented for maximum optimisation of data exchange between the CPU processors. The optimization intends maximum utilization of the possibilities given by the two-processor architecture of the CPUs. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The optimal structure should enable the processors to work in parallel as much as possible, and minimize the situation, when one processor has to wait for the other.
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References
M. Chmiel, E. Hrynkiewicz, Parallel bit-byte CPU structures of programmable logic controllers. In: International Workshop ECMS, Liberec, Czech Republic, pp. 67–71 (1999).
M. Chmiel, W. Ci⇂zyński, A. Nowara, Timers and counters applied in PLCs. In: International Conference PDS, Gliwice, Poland, pp. 165–172 (1995a).
M. Chmiel, L. Drewniok, E. Hrynkiewicz, Single board PLC based on PLDs. In: International Conference PDS, Gliwice, Poland, pp. 173–180 (1995b).
J. Donandt, Improving response time of Programmable Logic Controllers by use of a Boolean Coprocessor, IEEE Comput. Soc. Press., Washington, DC, USA, 4, pp. 167–169 (1989).
Z. Getko, Programmable Systems of Binary Control, Elektronizacja, WKiL, Warsaw (in Polish), 18:5–13 (1983).
E. Hrynkiewicz, Based on PLDs programmable logic controller with remote I/O groups. In: International Workshop ECMS, Toulouse, France, pp. 41–48
G. Michel, Programmable Logic Controllers, Architecture and Applications. John Wiley & Sons, West Sussex, England (1990).
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Chmiel, M., Hrynkiewicz, E. (2005). Remarks on Parallel Bit-Byte CPU Structures of the Programmable Logic Controller. In: Design of Embedded Control Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-28327-7_20
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DOI: https://doi.org/10.1007/0-387-28327-7_20
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-23630-8
Online ISBN: 978-0-387-28327-2
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