Abstract
Circuit realization on a single programmable logic array (PLA) may be unacceptable because of the large number of terms in sum-of-products; therefore a problem of block synthesis is considered in this paper. This problem is to realize a multilevel form of Boolean function system by some blocks, where each block is a PLA of smaller size. A problem of block synthesis in gate array library basis is also discussed in this paper. The results of experimental research of influence of previous partitioning of Boolean function systems on circuit complexity in PLA and gate array library basis are presented in this paper.
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Bibilo, P., Kirienko, N. (2005). Block Synthesis of Combinational Circuits. In: Design of Embedded Control Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-28327-7_16
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DOI: https://doi.org/10.1007/0-387-28327-7_16
Publisher Name: Springer, Boston, MA
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