Advanced Interfaces

10.5 Conclusion

The interface construct in SystemVerilog provides a powerful technique to group together the connectivity, timing, and functionality for the communication between blocks. In this chapter you saw how you can create a single testbench that connects to many different design configurations containing multiple interfaces. Your signal layer code can connect to a variable number of physical interfaces at run-time with virtual interfaces. Additionally, an interface can contain the procedural code that drives the signals and assertions to check the protocol.

In many ways, an interface can resemble a class with pointers, encapsulation, and abstraction. This lets you create an interface to model your system at a higher level than Verilog’s traditional ports and wires. Just remember to keep the testbench in the program block.