Impact of the address changing on the detection of pattern sensitive faults
This paper introduces a new concept for memory testing based on transparent memory tests in terms of pattern sensitive faults detection with different address order generation technique. It is commonly known, that only march tests can be in use now to test modern memory chips. Every march test algorithm can be applied in different ways and still be effective to detect target faults. Using properties of Degrees of Freedom in march testing  such as address changing, we can detect Pattern Sensitive Faults (PSF). Combination of march tests with proposed technique allows us to detect all memory faults, including PSF, with a high probability. Used tests are more effective and in many cases, experimental studies even show a higher efficiency of use of simple march tests in connection with proposed technique.
Keywordsmemory testing pattern sensitive faults march tests
Unable to display preview. Download preview PDF.
- A.J. Van de Goor, “Testing semiconductor memories, theory and practice”, John Wiley & Sons 1991, ISBN 0 471 92586 1.Google Scholar
- K.L. Cheng., C.W. Wu, “Neighborhood Pattern-Sensitive Fault Testing for Semiconductor Memories”, proc. VLSI Design/CAD Symp., Pingtung Aug. 2000, pp. 401–404.Google Scholar
- M. Nicolaidis, “Transparent BIST for RAMs”, Proc. IEEE Int. Test Conf., Baltimore, MD, Oct. 1992, pp. 598–607.Google Scholar
- D.K. Bhavsar, J.H. Edmondson, “Alpha 21164 Testability Strategy”, IEEE Design&Test, Vol. 14, No 1, January–March 1997, pp.25–33.Google Scholar
- D. Niggemeyer, J. Otterstedt, M. Redeker, “Detection of Non classical Memory Faults using Degrees of Freedom in March Testing”, Rec. 11th Workshop “Testmethods and Reliability of Circuits and Systems”, Potsdam, Feb. 1999.Google Scholar
- A.J. Van de Goor, G.N. Gaydadjiev, V.N. Yarmolik, V.G. Mikitjuk, “Memory Tests and their Fault Coverage into a New Perspective, Resulting into a New Test”, SEMICON, Seul, Korea, Jan. 1996.Google Scholar
- I. Mrozek, V.N. Yarmolik, “Detection of Pattern Sensitive Faults by Multiple Transparent March Tests”, Mixed Design of Integrated Circuits and Systems, proc. 10th International Conference, Lodz 26–28 June 2003-MIXDES'03, pp. 542–545.Google Scholar
- B. Sokół, V.N. Yarmolik, “Wpływ zmian porządku adresów i zawartości na efektywność testów pamięci”, proc. VII Krajowa Konferencja Naukowa, RUC'2004 Reprogramowalne Układy Cyfrowe”, Szczecin 13–14 May 2004.Google Scholar