Introduction and Motivation

11. Summary

This book makes a case as to why programmable platforms will enable the next design discontinuity. In particular we argue that system designers looking to realize system applications will increasingly eschew ASICs designed through an HDL-based synthesis methodology for programmable platforms. These programmable platforms are themselves assemblages of programmable components. Chris Rowen, Tensilica’s founder and CEO, has been quoted as saying: “The processor is the NAND gate of the future.” We paraphrase this to say: “ASIPs are the standard-cells of the future.” Both the gate-level design era of the 1980’s and the register-transfer level design era of the 1990’s relied heavily on well-designed standard cells. Similarly, we anticipate that the next design discontinuity will rely heavily on well-designed ASIPs as basic building blocks. However, we believe that the future success of ASIPs will depend on developing high-productivity design methodologies for ASIPs that produce efficient designs. Describing such a methodology is the goal of this book.