Skip to main content
SpringerLink
Log in
Book cover

Design of Very High-Frequency Multirate Switched-Capacitor Circuits pp 123–162Cite as

Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter

  • Chapter

  • 917 Accesses

Part of the book series: The International Series in Engineering and Computer Science ((SECS,volume 867))

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J.E. Franca, D.G. Haigh, “Design and Applications of Single-Path Frequency-Translated Switched-Capacitor Systems,” IEEE Trans. Circuits and Systems, Vol.35, No.4, pp.394–408, Apr.1988.

    Article  Google Scholar 

  2. D.H. Shen, C-M. Hwang, B.B. Lusignan, B.A. Wooley, “A 900-MHz RF Front-End with Integrated Discrete-Time Filtering,” IEEE J. Solid-State Circuits, Vol.31, No.12, pp.1945–1954, Dec.1996.

    Article  Google Scholar 

  3. P.J. Chang, A. Rofougaran, A.A. Abidi, “A CMOS channel-select filter for a direct-conversion wireless receiver,” IEEE J. Solid-State Circuits, Vol.32, pp.722–729, May 1997.

    Article  Google Scholar 

  4. R.F. Neves, J.E. Franca, “A CMOS Switched-Capacitor Bandpass Filter with 100 Msample/s Input Sampling and Frequency Downconversion,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp.248–251, Sep.2000.

    Google Scholar 

  5. Yi-Huei Chen, Jenn-Chyou Bor; Po-Chiun Huang, “A 2.5 V CMOS Switched-Capacitor channel-select filter with image rejection and automatic gain control,” in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers, pp.111–114, 2001.

    Google Scholar 

  6. L.K. Tan, H. Samueli, “A 200 MHz Quadrature digital Synthesizer/Mixer in 0.8μm CMOS,” IEEE J. Solid-State Circuits, vol.30, No.3, pp.193–199, Mar.1995.

    Article  Google Scholar 

  7. A. Edman, A. Björklid, I. Söderquist, “A 0.8μm CMOS 350 MHz Quadrature Direct Digital Frequency Synthesizer with Integrated D/A Converters,” Proc. IEEE 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp.54–55, 1998.

    Google Scholar 

  8. J. Vankka, M. Waltari, M. Kosunen, K.A.I. Halonen, “A Direct Digital Synthesizer with an On-Chip D/A-Converter,” IEEE J. Solid-State Circuits, vol.33, No.2, pp.166–176, Feb.1998.

    Article  Google Scholar 

  9. A. Madisetti, A.Y. Kwentus, A.N. Willson, Jr. “A 100-MHz, 16-b, Direct Digital Frequency Synthesizer with a 100-dBc Spurious-Free Dynamic Range,” IEEE J. Solid-State Circuits, vol.34, No.8, pp.1034–1042, Aug.1999.

    Article  Google Scholar 

  10. S. Mortezapour, E.K.F. Lee, “Design of Low-Power ROM-Less Direct Digital Frequency Synthesizer Using Nonlinear Digital-to-Analog Converter,” IEEE J. Solid-State Circuits, vol.34, No.10, pp.1350–1359, Oct.1999.

    Article  Google Scholar 

  11. J. Jiang, E.K.F. Lee, “A ROM-less Direct Digital Frequency Synthesizer Using Segmented Nonlinear Digital-to-Analog Converter,” Proc. IEEE Custom Integrated Circuits Conference, pp.165–168, May 2001.

    Google Scholar 

  12. Y.P. Tsividis, “Integrated continuous-time filter design-An overview,” IEEE J. Solid-State Circuits, vol.29, No.3, pp.166–176, Mar. 1994.

    Article  Google Scholar 

  13. N. Rao, V. Balan and R. Contreras, “A 3V 10–100-MHz Continuous-Time Seventh Order 0.05° Equiripple Linear Phase Filter”, in ISSCC Digest of Technical Papers, pp.44–46, Feb.1999.

    Google Scholar 

  14. R. Castello, I. Bietti, F. Svelto, “High-frequency filters in deep-submicron CMOS technology,” in ISSCC Digest of Technical Papers, pp74–75, Feb.1999.

    Google Scholar 

  15. José Moreira, Design Techniques for Low-Power, High Dynamic Range Continuous-Time Filters, Ph.D. Dissertation, Instituto Superior Técnico, Portugal, 1999.

    Google Scholar 

  16. G. Groenewold, “Low-power MOSFET-C 120 MHz Bessel allpass filter with extended tuning range,” IEE Proc. Circuits, Devices and Sys., vol.147, no.1, pp. 28–34, Feb.2000.

    Article  Google Scholar 

  17. Y.P. Tsividis, “Continuous-time filters in telecommunications chips,” IEEE Communications Magazine, pp.132–137, Apr. 2001.

    Google Scholar 

  18. G. Bollati, S. Marchese, M. Demicheli, R. Castello, “An Eighth-order CMOS low-Pass filter with 30–120 MHz tuning range and programmable boost,” IEEE J. Solid-State Circuits, Vol.36, No.7, pp.1056–1066, Jul.2001.

    Article  Google Scholar 

  19. A. Nagari, G. Nicollini, “A 3 V 10 MHz pseudo-differential SC bandpass filter using gain enhancement replica amplifier,” in ISSCC Digest of Technical Papers, pp.52–53, Feb.1997.

    Google Scholar 

  20. K.V. Hartingsveldt, P. Quinn, A.V. Roermund, “A. 10.7 MHz CMOS SC Radio IF Filter with Variable Gain and a Q of 55”, in ISSCC Digest of Technical Papers, pp152–153, Feb.2000.

    Google Scholar 

  21. J.E. Franca, R.P. Martins, “IIR Switched-Capacitor decimator building blocks with optimum implementation,” IEEE Trans. Circuits and Systems, Vol. CAS-37, No.1, pp.81–90, Jan. 1990.

    Article  MathSciNet  Google Scholar 

  22. R. Naiknawave, T.S. Fiez, “Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations,” IEEE J. of Solid-State Circuits, Vol.34, No.3, pp.304–317, Mar.1999.

    Google Scholar 

  23. Seng-Pan U, R.P. Martins, J.E. Franca, “Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems,” in Proc. The 2002 IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 2002.

    Google Scholar 

  24. J.M. Cohn, D.J. Garrod, R.A. Rutenbar, L.R. Carley, “KOAN/ANAGRAM II: New tools for device-level analog placement and routing,” IEEE J. of Solid-State Circuits, Vol.26, No.3, pp.330–342, Mar.1991.

    Article  Google Scholar 

  25. E. Malavasi, A. Sangiovanni-Vincentelli, “Area routing for analog layout,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.12, No.8, pp.1186–1197, Aug.1993.

    Article  Google Scholar 

  26. E. Malavasi, D. Pandini, “Optimum CMOS stack generation with analog constraints,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol.14, No.1, pp.107–122, Jan.1995.

    Article  Google Scholar 

  27. J.D. Bruce, H.W. Li, M.J. Dallabetta, R.J. Baker, “Analog layout using ALAS,” IEEE J. of Solid-State Circuits, Vol.31, No.2, pp.271–274, Feb.1996.

    Article  Google Scholar 

  28. D.A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.

    Google Scholar 

  29. R.J. Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1997.

    Google Scholar 

  30. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001.

    Google Scholar 

  31. M.J. McNutt, S. LeMarquis, J.L. Dunkley, “Systematic capacitance matching errors and correlative layout procedures,” IEEE J. of Solid-State Circuits, Vol.29, No.5, pp.611–616, May.1994.

    Article  Google Scholar 

  32. T.J. Schmerbeck, “Noise coupling in mixed signal ASICs,” Low-Power HF Microelectronics: A Unified Approach, Chapter 10, IEE Press, 1996.

    Google Scholar 

  33. AMS Analog Group, Crosstalk in Mixed-Signal Systems, AMS, 1996.

    Google Scholar 

  34. T. Blalack, Switching Noise In Mixed-Signal Integrated Circuits, Ph.D. Dissertation, Stanford University, USA, 1997.

    Google Scholar 

  35. B.R. Stanisic, N.K. Verghese, R.A. Rutenbar, L.R. Carley, D.J. Allstot, “Addressing substrate coupling in mixed-mode IC’s: simulation and power distribution synthesis,” IEEE J. of Solid-State Circuits, Vol.29, No.3, pp.226–237, Mar.1994.

    Article  Google Scholar 

  36. X. Aragonès, A. Rubio, “Experimental comparison of substrate noise coupling using different wafer types,” IEEE J. of Solid-State Circuits, Vol.34, No.10, pp.1405–1409, Oct.1999.

    Article  Google Scholar 

  37. Y. Zinzius, E. Lauwers, G. Gielen, W. Sansen, “Evaluation of the substrate noise effect on analog circuits in mixed-signal designs,” in Proc. South Southwest Symposium on Mixed-Signal Design (SSMSD), pp.131–134, 2000.

    Google Scholar 

  38. M.v. Heijningen, J. Compiet, P. Wambacq, S. Donnay, M.G.E. Engels, I. Bolsens, “Analysis and experimental verification of digital substrate noise generation for Epi-type substrates,” IEEE J. of Solid-State Circuits, Vol.35, No.7, pp.1002–1008, Jul.2000.

    Article  Google Scholar 

  39. M. Ingels. M.S.J. Steyaert, “Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-signal IC’s” IEEE J. of Solid-State Circuits, Vol.32, No.7, pp.1136–1141, Jul.1997.

    Article  Google Scholar 

  40. B. Nauta, G. Hoogzaad, “How to deal with substrate noise in analog CMOS circuits,” in Proc. European Conference on Circuits, Theory and Design (ECCTD), pp.12–1/6, 1997.

    Google Scholar 

  41. K. Falakshahi, High-Speed High-Resolution D/A Conversion in CMOS, Ph.D. Dissertation, Stanford University, USA, 1999.

    Google Scholar 

  42. M. Felder, J. Ganger, “Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: design strategies to minimize noise effects on a mixed-signal chip,” IEEE Trans. Circuits and Systems — II: Analog and Digital Signal Processing, Vol.46, No.11, pp.1427–1436, Nov. 1999.

    Article  Google Scholar 

  43. P. Larsson, “Measurements and analysis of PLL jitter caused by digital switching noise,” in Proc. European Solid-State Circuits Conference (ESSCIRC), Sep.2000.

    Google Scholar 

  44. D.K. Su, M.J. Loinaz, S. Masui, B.A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. of Solid-State Circuits, Vol.28, No.4, pp.420–429, Apr..1993.

    Article  Google Scholar 

  45. K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE J. of Solid-State Circuits, Vol.29, No.10, pp.1212–1219, Oct.1994.

    Article  Google Scholar 

  46. F.J.R. Clement, E. Zysman, M. Kayal, M. Declercq, “LAYIN: Toward a global solution for parasitic coupling modeling and visualization,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp.537–540, May 1994.

    Google Scholar 

  47. N.K. Verghese, D.J. Allstot, M.A. Wolfe, “Fast parasitic extraction for substrate coupling in mixed-signal ICs,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp.121–124, 1995.

    Google Scholar 

  48. K.J. Kerns, I.L. Wemple, A.T. Yang, “Efficient parasitic substrate modeling for monolithic mixed-A/D circuit design and verification,” Analog Integrated Circuits and Signal Processing, 10, pp.7–21, 1996.

    Article  Google Scholar 

  49. R. Gharpurey, R.G. Meyer, “Modeling and analysis of substrate coupling in integrated circuits,” IEEE J. of Solid-State Circuits, Vol.31, No.3, pp.344–353, Mar.1996.

    Article  Google Scholar 

  50. N.K. Verghese, D.J. Allstot, M.A. Wolfe, “Verification techniques for substrate coupling and their application to mixed-signal IC design,” IEEE J. of Solid-State Circuits, Vol.31, No.3, pp.354–365, Mar.1996.

    Article  Google Scholar 

  51. A. Samavedam, A. Sadate, K. Mayaram, T.S. Fiez, “A scalable substrate noise coupling model for design of mixed-signal IC’s,” IEEE J. of Solid-State Circuits, Vol.35, No.6, pp.895–904, Jun.2000.

    Article  Google Scholar 

  52. N.P. Van der Meijs, A.J. Van Genderen, F. Beeftink, P.J.H. Elias, SPACE User’s Manual, Department of Electrical Engineering — Delft University of Technology, The Netherland. URL: http://cas.et.tudelft.nl/~space/space.html.

    Google Scholar 

  53. L.K. Wang, H.H. Chen, “On-chip decoupling capacitor design to reduce switching-noise-induced instability in CMOS/SOI VLSI,” in Proc. 1995 IEEE International SOI Conference, pp.100–103, Oct.1995.

    Google Scholar 

  54. P. Larsson, “Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance,” IEEE J. of Solid-State Circuits, Vol.32, No.4, pp.574–576, Apr.1997.

    Article  MathSciNet  Google Scholar 

  55. Seng-Pan U, R.P. Martins, J.E. Franca, “A 2.5 V, 57 MHz, 15-Tap SC bandpass interpolating filter with 320 MHz output sampling rate in 0.35mm CMOS,” in ISSCC Digest of Technical Papers, Vol.45, pp380–381, San Francisco, USA, Feb. 2002.

    Google Scholar 

  56. Seng-Pan U, R.P. Martins and J.E. Franca, “A 2.5V 57MHz 15-Tap SC Bandpass Interpolating Filter with 320MHz Output Sampling Rate in 0.35mm CMOS,” IEEE J. of Solid-State Circuits, pp. 87–99, vol.39, January, 2004.

    Article  Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer

About this chapter

Cite this chapter

(2006). Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter. In: Design of Very High-Frequency Multirate Switched-Capacitor Circuits. The International Series in Engineering and Computer Science, vol 867. Springer, Boston, MA. https://doi.org/10.1007/0-387-26122-2_6

Download citation

  • DOI: https://doi.org/10.1007/0-387-26122-2_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-26121-8

  • Online ISBN: 978-0-387-26122-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation