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Design of Very High-Frequency Multirate Switched-Capacitor Circuits pp 69–97Cite as

Gain- and Offset- Compensation for Multirate SC Circuits

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References

  1. Christian C. Enz, G.C. Temes, “Circuit techniques for reducing the effects of Op-Amp imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization,” Proceeding of The IEEE, Vol.84, No.11, pp.1584–1614, Nov.1996.

    Article  Google Scholar 

  2. R.C. Yen, P.R. Gray, “A MOS Switched-Capacitor instrumentation amplifier,” IEEE J. Solid-State Circuits, Vol.SC-17, pp.1008–1013, 1982.

    Article  Google Scholar 

  3. Y. Huang, P. Ferguson, G.C. Temes, “Reduced Nonlinear Distortion in Circuits with Correlated Double Sampling,” IEEE Trans. Circuits and Systems — II: Analog and Digital Signal Processing, Vol.44, No.7, pp.593–597, Jul.1997.

    Article  MATH  Google Scholar 

  4. K.K.K. Lam, M.A. Copeland, “Noise-cancelling Switched-Capacitor filtering technique,” IEE Electronics Letters, Vol.19, No.20, pp.810–811, Sep.1983.

    Google Scholar 

  5. K. Haug, F. Maloberti, G.C. Temes, “Switched-Capacitor integrators with low finite-gain sensitivity,” IEE Electronics Letters, Vol.21, No.24, pp.1156–1157, Nov.1985.

    Google Scholar 

  6. K. Haug, F. Maloberti, G.C. Temes, “Switched-Capacitor circuits with low op-amp gain sensitivity,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), No.24, pp.797–800, May.1986.

    Google Scholar 

  7. K. Nagaraj, K. Singhal, T.R. Viswanathan, J. Vlach, “Reduction of finite-gain effect in Switched-Capacitor filters,” IEE Electronics Letters, Vol.21, No.15, pp.644–645, Jul.1985.

    Google Scholar 

  8. Wing-Hung Ki, G.C. Temes, “Offset-Compensated Switched-Capacitor Integrator,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.2829–31, 1990.

    Google Scholar 

  9. Wing-Hung Ki, G.C. Temes, “Gain-and Offset-compensated Switched-Capacitor filters,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.1561–15664, 1991.

    Google Scholar 

  10. L.E. Larson, K.W. Martin, G.C. Temes, “GaAs Switched-Capacitor circuits for high-speed signal processing,” IEEE J. Solid-State Circuits, Vol.SC-22, No.6, pp.971–980, Dec.1987.

    Article  Google Scholar 

  11. A. Nagari, A. Baschirotto, F. Montecchi, R. Castello, “A 10.7-MHz Bi-CMOS high-Q double-sampled SC bandpass filter,” IEEE J. Solid-State Circuits, Vol.SC-32, No.10, pp.1491–1498, Oct.1997.

    Article  Google Scholar 

  12. L.E. Larson, G.C. Temes, “Switched-Capacitor gain stage with reduced sensitivity to finite amplifier gain and offset voltage,” IEE Electronics Letters, Vol.22, pp.1281–82, Nov.1985.

    Google Scholar 

  13. K. Nagaraj, T.R. Viswanathan, K. Singhal, J. Vlach, “Switched-Capacitor circuits with reduced sensitivity to amplifier gain,” IEEE Trans. on Circuits and Systems, Vol.CAS-34, pp.571–574, May 1987.

    Article  Google Scholar 

  14. H. Shafeeu, A.K. Betts, J.T. Taylor, “Novel amplifier gain insensitive Switched Capacitor integrator with same sample correction properties,” IEE Electronics Letters, Vol.27, No.24, pp.2277–2279, Nov.1991.

    Google Scholar 

  15. G. Palmisano, G. Palumbo, “High-frequency differential SC integrator with highly accurate gain compensation,” International J. of Circuit Theory and Applications, Vol.22, pp.71–75, 1994.

    Google Scholar 

  16. G.C. Temes, Huang Yunteng, P.F. Ferguson, “A high-frequency track-and-hold stage with offset and gain compensation,” IEEE Trans. on Circuits and Systems-II, Vol.42, pp.559–561, Aug 1995.

    Article  Google Scholar 

  17. J.A. Grilo, G.C. Temes, “Predictive correlated double sampling Switched-capacitor integrators,” in Proc. International Conference on Electronics, Circuits and Systems (ICECS), vol.2, pp.9–12, Sep. 1998.

    Google Scholar 

  18. Huang Yunteng, G.C. Temes, P.F. Ferguson, “Offset-and gain-compensated track-and-hold stages,” in Proc. International Conference on Electronics, Circuits and Systems (ICECS), vol.2, pp.13–16, Sep. 1998.

    Google Scholar 

  19. Xiaojing Shi, H. Matsumoto, K. Murao, “Gain-and offset-compensated non-inverting SC circuits,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, pp.425–428, 2000.

    Google Scholar 

  20. P. Gillingham, “Stray-free Switched-Capacitor unit-delay circuit,” IEE Electronics Letters, Vol.20, No.7, pp.308–310, Mar 1984.

    Google Scholar 

  21. K. Nagaraj, “Switched-Capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance,” IEE Electronics Letters, Vol.20, No.16, pp.663–664, 1984.

    Google Scholar 

  22. A.E. Said, “Stray-free Switched-Capacitor building block that realizes delay, constant multiplier, or summer Circuit,” IEE Electronics Letters, Vol.21, No.4, pp.167–168, Feb.1985.

    Google Scholar 

  23. A. Dabrowski, U. Menzi, G.S. Moschytz, “Offset-compensated Switched-Capacitor delay circuit that is insensitive to stray capacitance and to capacitor mismatch,” IEE Electronics Letters, Vol.25, No.10, pp.623–625, May 1989.

    Google Scholar 

  24. J.J.F. Rijns,. H. Wallinga, “Stray-insensitive switched-capacitor sample-delay-hold buffers for video frequency applications,” IEE Electronics Letters, Vol.27 Issue: 8, pp.638–640, Apr.1991.

    Google Scholar 

  25. S. Eriksson, “Realization of Switched-Capacitor delay lines and Hilbert transformers,” IEE Electronics Letters, Vol.27, No.14, pp.1262–1264, Jul.1991.

    Google Scholar 

  26. Hiroshi Iwakura, “Realization of Tapped Delay Lines Using Switched-Capacitor LDI Ladders and Application to FIR Filter Design,” IEEE Trans. on Circuits and Systems-II, Vol.40, pp.794–797, Dec. 1993.

    Article  Google Scholar 

  27. Seng-Pan U, R.P. Martins, J.E. Franca, “Highly accurate mismatch-free SC delay Circuits with reduced finite gain and offset sensitivity,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vol.2, pp.57–60, USA, May 1999.

    Google Scholar 

  28. Seng-Pan U, R.P. Martins, J.E. Franca, “Offset-and gain compensated and mismatch-free SC delay circuit with flexible implementation,” IEE Electronics Letters, Vol.35, No.3, pp.188–189, Feb. 1999.

    Article  Google Scholar 

  29. K. Martin, A.S. Sedra, “Effects of the Op-Amp finite gain and bandwidth on the performance of Switched-Capacitor filters,” IEEE Trans. on Circuits and Systems, Vol.CAS-28, pp.822–829, Aug.1981.

    Article  Google Scholar 

  30. A.C.M. Queiroz, P.M. Pinheiro, L.P. Calôba, “Systematic nodal analysis of switched-current filters,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1801–1804, Jun. 1991.

    Google Scholar 

  31. K. Suyama, S.C. Fang, “User’s Manual of SWITCAP2 Version 1.1,” Columbia University, 1992.

    Google Scholar 

  32. G. Chang, A. Rofougaran, Mong-Kai Ku, A.A. Abidi, H. Samueli, “A Low-Power CMOS Digitally Synthesized 0–13MHz Agile Sinewave Generator,” in IEEE ISSCC Digest of Technical Paper, pp.32–33. Feb. 1994.

    Google Scholar 

  33. A. Rofougaran, G. Chang, J.J. Rael, J.Y.-C. Chang, M. Rofougaran, P.J. Chang, M. Djafari, M-K Ku, E.W. Roth, A.A. Abidi, H. Samueli, “A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in 1-µm CMOS-Part I: Architecture and Transmitter Design.” IEEE J. of Solid-State Circuits, Vol.33, No.4, pp.515–534, Apr.1998.

    Article  Google Scholar 

  34. Seng-Pan U, R.P. Martins, J.E. Franca, “A 120 MHz SC 4th-Order Elliptic Interpolation Filter with Accurate Gain and Offset Compensation For Direct Digital Frequency Synthesizer,” in Proc. The First IEEE Asia-Pacific Conference on ASICs (APASIC’ 99), pp.1–4, Aug.1999.

    Google Scholar 

  35. R.E. Crochiere, L.R. Rabiner, Multirate Digital Signal Processing, Prentice-Hall, Inc., NJ, 1983.

    Google Scholar 

  36. J.E. Franca, R.P. Martins, “IIR Switched-Capacitor decimator building blocks with optimum implementation,” IEEE Trans. Circuits and Systems, Vol. CAS-37, No.1, pp.81–90, Jan. 1990.

    Article  MathSciNet  Google Scholar 

  37. R.P. Martins, J.E. Franca, F. Maloberti, “An optimum CMOS Switched-Capacitor antialiasing decimating filter,” IEEE J. Solid-State Circuits, Vol.28 No.9, pp.962–970, Sep. 1993.

    Article  Google Scholar 

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(2006). Gain- and Offset- Compensation for Multirate SC Circuits. In: Design of Very High-Frequency Multirate Switched-Capacitor Circuits. The International Series in Engineering and Computer Science, vol 867. Springer, Boston, MA. https://doi.org/10.1007/0-387-26122-2_4

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  • DOI: https://doi.org/10.1007/0-387-26122-2_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-26121-8

  • Online ISBN: 978-0-387-26122-5

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