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References

  1. Z.Q. Shang, J.I. Sewell, “Development of efficient switched network and mixed-mode simulator,” IEE Proc. Circuits, Devices and Systems, Vol.145, No.1, pp.24–34, Feb. 1998.

    Article  Google Scholar 

  2. A. Petraglia, S.K. Mitra, “Effects of coefficient inaccuracy in switched-capacitor transversal filters,” IEEE Trans. Circuits and Systems, Vol.38, No.9, pp.977–983, Sep. 1991.

    Article  Google Scholar 

  3. A. Petraglia, “Fundamental frequency response bounds of direct-form recursive switched-capacitor filters with capacitance mismatch,” IEEE Trans. Circuits and Systems — II: Analog and Digital Signal Processing, Vol.48, No.4, pp.340–350, Apr. 2001.

    Article  Google Scholar 

  4. A. Petraglia, Mixed Analog/Digital Structures for High-Speed A/D Conversion and Signal Processing, Ph.D. Dissertation, University of California, Santa Barbara, USA, 1991.

    Google Scholar 

  5. A. Petraglia, S.K. Mitra, “Analysis of mismatch Effects among A/D converters in a time-interleaved waveform digitizer,” IEEE Trans. Instrumentation and Measurement, Vol.40, No.5, pp.831–835, Oct. 1991.

    Article  Google Scholar 

  6. Y.C. Jenq, “Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High-Speed Waveform Digitizers,” IEEE Trans. Instrumentation and Measurement, vol.37, no.2, pp.245–251, Jun.1988.

    Article  Google Scholar 

  7. G.T. Uehara, Circuit techniques and considerations for implementation of high speed CMOS analog-to-digital interfaces for DSP-based PRML magnetic disk read channels, Ph.D. Dissertation, University of California, Berkeley, USA, 1993.

    Google Scholar 

  8. M. Gustavssn, CMOS A/D converters for telecommunications, Ph.D. Dissertation, Linköping Universitet, Sweden, 1998.

    Google Scholar 

  9. N. Kurosawa, H. Kobayashi, K. Maruyama, et al., “Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems,” IEEE Trans. Circuits and Systems — I, vol.48, No.3, pp.261–271, Mar.2001.

    Article  Google Scholar 

  10. Wing-Hung Ki, G.C. Temes, “Gain-and Offset-compensated Switched-Capacitor filters,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.1561–15664, 1991.

    Google Scholar 

  11. A. Yu, W.C. Black, Jr., “Error Analysis for time-interleaved analog channels,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vol.I, pp.468–471, May 2001.

    Google Scholar 

  12. M. Gustavsson, N.N. Tan, “A global passive sampling technique for high-speed Switched-Capacitor time-interleaved ADCs,” IEEE Trans. Circuits and Systems — II: Analog and Digital Signal Processing, vol.47, No.9, pp.821–831, Sep.2000.

    Article  Google Scholar 

  13. Y.C. Jenq, “Digital-To-Analog (D/A) converters with nonuniformly sampled signals,” IEEE Trans. Instrumentation and Measurement, vol.45, No.1, pp.56–59, Feb.1996.

    Article  Google Scholar 

  14. Y.C. Jenq, “Direct digital synthesizer with jittered clock,” IEEE Trans. Instrumentation and Measurement, vol.46, No.3, pp.653–655, Jun. 1997.

    Article  Google Scholar 

  15. Seng-Pan U, R.P. Martins, J.E. Franca, “Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.441–444, May. 2002.

    Google Scholar 

  16. Sai-Weng Sin, Seng-Pan U, and R.P. Martins, “Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.I-129–I-132 vol.1, May 2003.

    Google Scholar 

  17. Seng-Pan U, Sai-Weng Sin and R.P. Martins, “Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches,” Proc. IEEE Instrumentation and Measurement Technology Conference-IMTC’2003, vol. 2, pp. 1298–1301, May 2003.

    Google Scholar 

  18. Seng-Pan U, Sai-Weng Sin and R. P. Martins, “Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects,” IEEE Transactions on Instrumentation and Measurement, vol. 53, pp. 1279–1299, Aug. 2004.

    Article  Google Scholar 

  19. Sai-Weng Sin, Seng-Pan U and R.P. Martins, “Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals,” in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing — “ICASSP’2003”, vol. 6, pp. VI-253–256, April 2003.

    Google Scholar 

  20. H. Kobayashi, M. Morimura, et al., “Aperture jitter effects in wideband sampling systems,” in Proc. of IEEE Instrumentation and Measurement Technology Conference — IMTC’99, pp.880–885, May 1999.

    Google Scholar 

  21. J.L. González, E. Alarcón, “Clock-jitter induced distortion in high speed CMOS Switched-Current segmented digital-to-analog converters,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.512–515, May 2001.

    Google Scholar 

  22. C.A. Gobet, A. Knob, “Noise analysis of Switched Capacitor networks,” IEEE Trans. Circuits and Systems, vol.CAS-30, No.1, pp.37–43, Jan.1983.

    Article  Google Scholar 

  23. R. Castello, P.R. Gray, “Performance limitations in Switched-Capacitor filters,” IEEE Trans. Circuits and Systems, vol.CAS-32, No.9, pp.865–876, Sep.1985.

    Article  Google Scholar 

  24. R. Gregorian, G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons, Inc., 1986.

    Google Scholar 

  25. J. Goette, W. Guggenbühl, “Noise performance of SC-Integrators assuming different operational transconductance amplifier (OTA) models,” IEEE Trans. Circuits and Systems, vol.35, No.8, pp.1042–1048, Aug.1988.

    Article  MathSciNet  Google Scholar 

  26. A.K. Ong, Bandpass Analog-to-Digital Conversion for Wireless Applications, Ph.D. Dissertation, Standford University, USA, 1998.

    Google Scholar 

  27. J. Grilo, Improved Design Techniques for Low-Voltage Low-Power Switched-Capacitor Delta-Sigma Modulator, Ph.D. dissertation, Oregon State University, USA, 1997.

    Google Scholar 

  28. A. Marques, High-speed CMOS data converters, Ph.D. dissertation, Katholieke Universiteit Leuven, Belgium, 1999.

    Google Scholar 

  29. R.A. Gomez, A Discrete-Time Analog Read Channel IC for Magnetic Recording, Ph.D. Dissertation, University of California, Los Angeles, USA, 1993.

    Google Scholar 

  30. D.H. Shen, Architecture and Design of a Monolithic Radio Frequency Receiver, Ph.D. Dissertation, Stanford University, USA, 1997.

    Google Scholar 

  31. T. Cho, Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures, Ph.D. Dissertation, University of California, Berkeley, USA 1995.

    Google Scholar 

  32. K.Y. Kim, A 10-bit, 100MS/s Analog-to-Digital Converter in 1-μm CMOS, Ph.D. Dissertation, University of California, Los Angeles, USA, 1996.

    Google Scholar 

  33. A.M. Abo, Design for Reliability of Low-voltage, Switched-Capacitor Circuits, Ph.D. Dissertation, University of California, Berkeley, USA, 1999.

    Google Scholar 

  34. J. Goes, Optimization of Self-Calibrated CMOS Pipelined Analogue-to-Digital Converters, Ph.D. Dissertation, Instituto Superior Técnico, Portugal, 2000.

    Google Scholar 

  35. M. Gustavsson, J.J. Wikner, N.N. Tan, CMOS Data Converters for Communications, Kluwer Academic Publishers, 2000.

    Google Scholar 

  36. K.R. Laker, W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, Inc., 1994.

    Google Scholar 

  37. D.A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.

    Google Scholar 

  38. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th-edition, John Wiley & Sons, Inc., 2001.

    Google Scholar 

  39. A. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001.

    Google Scholar 

  40. R.J. Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1997.

    Google Scholar 

  41. P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, 2nd-edition, Oxford University Press, Inc., 2002.

    Google Scholar 

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(2006). Practical Multirate SC Circuit Design Considerations. In: Design of Very High-Frequency Multirate Switched-Capacitor Circuits. The International Series in Engineering and Computer Science, vol 867. Springer, Boston, MA. https://doi.org/10.1007/0-387-26122-2_3

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  • DOI: https://doi.org/10.1007/0-387-26122-2_3

  • Publisher Name: Springer, Boston, MA

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