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References
M. F. Toner and G. W. Roberts, “Histogram-Based Testing of a Sigma-Delta ADC”, Proceedings, 32nd Midwest Symposium on Circuits and Systems, Washington, pp. 760–763, Aug. 1992.
S.D. Millman, “Improving quality: yield versus test coverage”, Journal of Electronic Testing: Theory and Applications, pp. 253–261, 1994.
C. Mauder and R. Tulloss, The Test Access Port and Boundary Scan Architecture, IEEE Computer Society Press Tutorial, 1990.
A. Grochowski, D. Bhattacharya, T.R. Viswanathan and K. Laker, “Integrated Circuit Testing for Quality Assurance in Manufacturing: History, Current Status and Future Trends”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 44, pp. 610–633, August 1997.
K. Baker, A.M. Richardson and A.P. Dorey, “Mixed signal test-techniques, applications and demands”, IEE Proceedings-G, Circuits, Devices and Systems, Vol. 143, pp. 358–365, Dec. 1996.
F.G.M. de Jong, “Analogue system testability: an industrial perspective”, Proceedings, AMATIST ESPRIT Open Workshop, Twente, May 1997.
S. Sunter, “Mixed-Signal BIST — Does Industry Need it?”, Proceedings, 3rd IEEE International Mixed Signal Workshop, Tutorial 2, Seattle, June 1997.
Semiconductor Industry Association (SIA). The National Technology Roadmap for Semiconductors, 1997.
M.H. Costin, “On-board diagnostics of vehicle emission system components: review of upcoming government regulation”, Proceedings, IFAC Fault Detection, Supervision and Safety for Technical Processes, Baden-Baden, pp. 497–501, 1991.
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, New York: Computer Science Press, 1990.
K. D. Wagner and T. W. Williams, “Design for testability of analog/digital networks”, IEEE Transactions on Industrial. Electronics, Vol. 36, pp. 227–230, May 1989.
J.A Prieto, A Rueda, I Grout, E Peralias, J L Huertas and A M Richardson, “An Approach to Realistic Fault prediction and Layout Design for Testability in Analogue Circuits” Proceedings, Design, Automation & Test in Europe Conference, Paris, pp. 905–912, Feb. 1998.
B. Atzema and T. Zwemstra, “Exploit Analog IFA to improve Specification Based Tests” Proceedings, European Design and Test Conference, Paris, paper 10C-1, March 1996.
A. Lechner, A. Richardson, B. Hermes and M. Ohletz “A Design for Testability Study on a High Performance Automatic Gain Control Circuit”, Proceedings, 16th IEEE VLSI Test Symposium (VTS98), Monterey, California, pp. 376–385, April 1998.
J.M. Soden, C.F. Hawkins, R.K. Gulati, and W. Mao, “IDDQ Testing: A Review,” Journal of Electronic Testing: Theory and Applications, Vol. 3, pp. 5–17, 1992.
A.H. Bratt, R.J. Harvey, A.P. Dorey and A.M. Richardson “Aspects of Current Reference Generation and Distribution for IDDx Pass/Fail Current Determination” Proceedings, IEE Colloquium on Mixed Signal VLSI Test, London, Digest no 1993/240, pp. 3/1–3/8, Dec 1993.
Andrew Richardson, Adrian Bratt, Iluminada Baturone and Jose Luis Huertas “The Application of IDDX Test Strategies in Analogue and Mixed Signal IC’s”, Proceedings, IEEE Mixed Signal Test Workshop, Grenoble, pp.206–211, June 1995.
J.P.M van Lammeren, “ICCQ: A Test Method for Analogue VLSI Based on Current Monitoring”, Proceedings, IEEE International Workshop on IDDQ Testing, Washington DC, pp. 24–29, November 1997.
P.S.A. Evans, M.A. Al-Qutayri, and P.R. Sheperd, “A novel technique for testing mixed-signal ICs”, Proceedings, European Test Conference, Munich, Germany, pp. 301–306, April 1991.
G. Russell and D.S. Learmonth, “Systematic approaches to testing embedded analogue circuit functions”, Microelectronics Journal, Vol. 25, pp. 133–138, March 1994.
IEEE P1149.4 proposal “Standard for Mixed Signal Test Bus” March 1995, IEEE Standards Department, 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA.
J.S. Matos, A.C. Leao, and J.C. Ferreira, “Control and observation of analog nodes in mixed-signal boards”, Proceedings, International Test Conf., Baltimore, pp. 323–331, October 1993.
L. Wurtz, “Built-in self-test structure for mixed-mode circuit”, IEEE Transactions on Instrumentation and Measurement, Vol. 42, pp. 25–29, Feb. 1993.
A. H. Bratt, A. M. D. Richardson, R. J. A. Harvey, and P. Dorey: “A design-for-test structure for optimising analogue and mixed signal IC test”, Proceedings, European Design and Test Conference, Paris, pp. 24–32, March 1995.
D. Vazquez, A. Rueda and J.L. Huertas, “A DfT methodology for active anaolgue filters”, Proceedings, IEEE Mixed Signal Test Workshop, Grenoble, June 1995.
D. Vázquez, A. Rueda, J. L. Huertas and E. PeralÍas. “A high-Q bandpass fully differential SC filter with enhanced testability”, Proceedings, European Solid State Circuit Conference (ESSCIRC’97), Southampton, pp. 260–263, Sep. 1997.
V. Kolarik, M. Lubaszewski, and B. Courtois, “Designing self-exercising analogue checkers”, Proceedings, VLSI Test Symposium, 1994, pp. 252–257.
A. Lechner, A. Richardson, A. Perkins, M. Zwolinski and B. Hermes, “Design for Testability Strategies for a High Performance Automatic Gain Control Circuit”, Proceedings, 4th IEEE International Mixed Signal Testing Workshop (IMSTW98), The Hague, The Netherlands, June 1998.
K. Parker, The Boundary-Scan Handbook, Kluwer Academic Publishers, Massachusetts, 1992.
R. Mason, B. Simon and K. Runtz, “Integrated Circuit Signal Measurements using an undersampling approach,” IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, pp. 1502–1504, Nov. 1998.
S. Sunter, “A low cost 100 MHz analog test bus,” Proceedings, IEEE VLSI Test Symposium, pp. 60–63, 1995.
K. Lofstrom, “A demonstration IC for the P1149.4 mixed-signal test standard,” Proceedings, IEEE International Test Conference, pp. 92–98, Oct. 1996.
V. Agrawal, C. Kime and K. Saluja, “A Tutorial on Built-In Self-Test”, IEEE Design and Test of Computers, pp. 73–80, March 1993 and pp. 69–77, June 1993.
P. Bardell, W. McAnney and J. Savir, Built-in Test for VLSI, Pseudorandom Techniques. John Wiley & Sons, New York, 1987.
S. Gupta and, D. Pradhan, “Can concurrent Checkers help BIST?”, Proceedings, International Test Conference, Baltimore, pp. 140–150, Sept. 1992.
B. Nadeau-Dostie, D. Burek and A. Hassan, “ScanBist: A Multifrequency Scan-Based BIST Method”, IEEE Design and Test of Computers, pp. 7–17, Spring 1994.
M. Lubaszewski, B. Courtois, “On the Design of Self-Checking Boundary Scannable Boards”, Proceedings, International Test Conference, Baltimore, pp. 372–381, Sept. 1992.
B. Könemann, B. Bennetts, N. Jarwala and B. Nadeau-Dostie, “Built-In Self-Test: Assuring System Integrity”, IEEE Computer, Vol. 29, pp. 39–45, November 1996.
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(2005). Design for Testability and Built-In Self-Test. In: Fault Diagnosis of Analog Integrated Circuits. Frontiers in Electronic Testing, vol 30. Springer, Boston, MA. https://doi.org/10.1007/0-387-25743-8_5
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